AS3709 datasheet(12/74 Pages) AMSCO

12 / 74 page

AS3709 – 12

ams Datasheet, Confidential: 2013-Aug [1-02]

D e t a i l ed D e scr i pt io n - P o w e r M a na ge me nt F u n c ti o n s

Fast Regulation Mode

This mode can be used to react faster on sudden load changes

and thus minimize the over-/undershoot of the output voltage.

This mode needs a 22uF output capacitor instead the 10uF one

to guarantee the stability of the regulator.

The mode is enabled by setting sd_fast =1.

Selectable Frequency Operation

Especially for very low load conditions, e.g. during a sleep mode

of a processor, the switching frequency can be reduced to

achieve a higher efficiency. The frequency can be set to 2, 3 or

4MHz and this mode is selected by setting sd_freq and sd_fsel

to the appropriate values.

100% PMOS ON Mode for Low Dropout Regulation

For low input to output voltage difference the DCDC converter

can use 100% duty cycle for the PMOS transistor, which is then

in LDO mode.

Step Down Converter Configuration Modes

The step down dc/dc converters have two configuration modes

to deliver different output currents for the applications. The

operating mode is selected by setting the bit sd2_slave,

sd4_slave and sd5_slave (the default is set by the Boot-OTP).

Figure 11:

DCDC Step Down Normal Operating Mode

Normal Operating Mode: sd2_slave = 0, sd4_slave = 0, sd5_slave = 0

DCDC

Step Down 3

VSUP_SD3

LX_SD3

FB_SD3

PVSS_SD3

2.2uF

1uH

10uF

VSUP

DCDC

Step Down 4

VSUP_SD4

LX_SD4

FB_SD4

PVSS_SD4

2.2uF

1uH

10uF

VSUP

DCDC

Step Down 5

VSUP_SD5

LX_SD5

FB_SD5

PVSS_SD5

2.2uF

1uH

10uF

VSUP

DCDC

Step Down 1

VSUP_SD1

LX_SD1

FB_SD1

PVSS_SD1

VSUP

10uF

2.2uF

SD1

0.6 – 3.3V

0.7 – 1A

1uH

DCDC

Step Down 2

VSUP_SD2

LX_SD2

FB_SD2

PVSS_SD2

VSUP

10uF

2.2uF

1uH

5 x 1A

SD2

0.6 – 3.3V

0.7 – 1A

SD3

0.6 – 3.3V

0.7 – 1A

SD4

0.6 – 3.3V

0.7 – 1A

SD5

0.6 – 3.3V

0.7 – 1A

AS3709 Datasheet(PDF) 12 Page - ams AG

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