ARM920T datasheet(29/350 Pages) ATMEL

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Programmer’s Model

ARM DDI 0151C

2-3

2.2

About the ARM9TDMI programmer’s model

The ARM9TDMI processor core implements ARM architecture v4T, and executes the

ARM 32-bit instruction set and the compressed Thumb 16-bit instruction set. The

programmer’s model is fully described in the ARM Architecture Reference Manual. The

ARM9TDMI Technical Reference Manual gives implementation details, including

instruction execution cycle times.

ARMv4T specifies a small number of implementation options. The options selected in

the ARM9TDMI implementation are listed in Table 2-1. For comparison, the options

selected for the ARM7TDMI implementation are also shown.

The ARM9TDMI is code-compatible with the ARM7TDMI, with two exceptions:

•

The ARM9TDMI core implements the base restored Data Abort model. This

significantly simplifies the software Data Abort handler.

•

The ARM9TDMI fully implements the instruction set extension spaces added to

the ARM (32-bit) instruction set in ARMv4 and ARMv4T.

These differences are explained in more detail in the following sections:

•

Data Abort model on page 2-3

•

Instruction set extension spaces on page 2-4.

2.2.1

Data Abort model

The base restored Data Abort model differs from the base updated Data Abort model

implemented by ARM7TDMI.

The difference in the Data Abort models affects only a very small section of operating

system code, the Data Abort handler. It does not affect user code. With the base restored

Data Abort model, when a Data Abort exception occurs during the execution of a

memory access instruction, the base register is always restored by the processor

hardware to the value the register contained before the instruction was executed. This

removes the requirement for the Data Abort handler to unwind any base register update

that might have been specified by the aborted instruction.

Table 2-1 ARM9TDMI implementation options

Processor

core

Architecture

Data Abort

model

Value stored by direct STR,

STRT, and STM of PC

ARM7TDMI

ARMv4T

Base updated

Address of instruction + 12

ARM9TDMI

ARMv4T

Base restored

Address of instruction + 12

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