ARM920T datasheet(33/350 Pages) ATMEL

33 / 350 page

Programmer’s Model

ARM DDI 0151C

2-7

In all cases, reading from, or writing any data values to any CP15 registers, including

those fields specified as unpredictable or should be zero, does not cause any permanent

damage.

All CP15 register bits that are defined and contain state, are set to zero by BnRES

except the V bit in register 1, which takes the value of macrocell input VINITHI when

BnRES is asserted.

You can only access CP15 registers with MRC and MCR instructions in a privileged mode.

The instruction bit pattern of the MCR and MRC instructions is shown in Figure 2-1. The

assembler for these instructions is:

MCR/MRC{cond} P15,opcode_1,Rd,CRn,CRm,opcode_2

Figure 2-1 CP15 MRC and MCR bit pattern

Instructions CDP, LDC, and STC, together with unprivileged MRC and MCR instructions to

CP15, cause the undefined instruction trap to be taken. The CRn field of MRC and MCR

instructions specifies the coprocessor register to access. The CRm field and opcode_2

fields specify a particular action when addressing registers. The L bit distinguishes

between an MRC (L=1) and an MCR (L=0).

Note

Attempting to read from a nonreadable register, or to write to a nonwritable register

causes unpredictable results.

The opcode_1, opcode_2, and CRm fields should be zero, except when the values specified

are used to select the desired operations, in all instructions that access CP15. Using

other values results in unpredictable behavior.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210

1110

1111

CRm

opcode_2

CRn

opcode_1

Cond

ARM920T Datasheet(PDF) 33 Page - ATMEL Corporation