ARM920T datasheet(63/350 Pages) ATMEL

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Memory Management Unit

ARM DDI 0151C

3-11

Section descriptor bit assignments are described in Table 3-4.

3.3.5

Coarse page table descriptor

A coarse page table descriptor provides the base address of a page table that contains

level two descriptors for either large page or small page accesses. Coarse page tables

have 256 entries, splitting the 1MB that the table describes into 4KB blocks. Figure 3-6

shows the format of a coarse page table descriptor.

Figure 3-6 Coarse page table descriptor

Note

If a coarse page table descriptor is returned from the level one fetch, a level two fetch is

initiated.

Table 3-4 Section descriptor bits

Bits

Description

31:20

Form the corresponding bits of the physical address for a section

19:12

Always written as 0

11:10

(AP) Specify the access permissions for this section

Always written as 0

8:5

Specify one of the 16 possible domains (held in the domain access control register)

that contain the primary access controls

Should be written as 1, for backward compatibility

3:2

These bits (C and B) indicate whether the area of memory mapped by this section is

treated as write-back cachable, write-through cachable, noncached buffered, or

noncached nonbuffered

1:0

These bits must be 10 to indicate a section descriptor

10 98

543210

Coarse page table base address

Domain

0 1

SBZ

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