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ARM920T Datasheet(PDF) 49 Page - ATMEL Corporation |
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ARM920T Datasheet(HTML) 49 Page - ATMEL Corporation |
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49 / 350 page ![]() Programmer’s Model ARM DDI 0151C Copyright © 2000, 2001 ARM Limited. All rights reserved. 2-23 Table 2-19 shows the instructions you can use to access the TLB lockdown register. Figure 2-8 shows the format of bits in register 10. Figure 2-8 Register 10 The entries in the TLBs are replaced using a round-robin replacement policy. This is implemented using a victim counter that counts from entry 0 up to 63, and then wraps back round to the base value and continues counting, wrapping around to the base value from 63 each time. There are two mechanisms available for ensuring entries are not removed from the TLB: • Locking an entry down prevents it from being selected for overwriting during a table walk. You can do this by programming the base value to which the victim counter reloads. For example, if the bottom 3 entries (0–2) are to be locked down, you must program the base counter to 3. • You can preserve an entry during an Invalidate All instruction. You can do this by ensuring the P bit is set when the entry is loaded into the TLB. Examples that show how you can load a single entry into the I and D TLBs at location 0, make it immune to Invalidate All, and lock it down are shown in Example 2-3 on page 2-24 and Example 2-4 on page 2-24. Table 2-19 Accessing the TLB lockdown register 10 Function Data Instruction Read D TLB lockdown TLB lockdown MRC p15,0,Rd,c10,c0,0 Write D TLB lockdown TLB lockdown MCR p15,0,Rd,c10,c0,0 Read I TLB lockdown TLB lockdown MRC p15,0,Rd,c10,c0,1 Write I TLB lockdown TLB lockdown MCR p15,0,Rd,c10,c0,1 31 26 25 20 19 1 0 Base SBZ/UNP P Victim |
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