ARM920T datasheet(47/350 Pages) ATMEL

47 / 350 page

Programmer’s Model

ARM DDI 0151C

2-21

Note

Only bits [31:26] are returned. Bits [25:0] are unpredictable.

Writing CP15 register 9 updates the cache lockdown register, both the base and the

current victim pointer for all cache segments. Bits [25:0] should be zero.

The victim counter specifies the cache line to be used as the victim for the next linefill.

This is incremented using either a random or round-robin replacement policy,

determined by the state of the RR bit in register 1. The victim counter generates values

in the range (base to 63). This locks lines with index values in the range (0 to base-1).

If base = 0, there are no locked lines.

Writing to CP15 register 9 updates the base pointer and the current victim pointer. The

next linefill uses, and then increments, the victim pointer. The victim pointer continues

incrementing on linefills, and wraps around to the base pointer. For example, setting the

base pointer to 0x3 prevents the victim pointer from selecting entries 0x0 to 0x2, locking

them into the cache. Example 2-1 shows how you can load a cache line into ICache line

0 and lock it down.

Example 2-1 Load a cache line into ICache line 0 and lock it down

MCR to CP15 register 9, opcode_2 = 0x1, Victim=Base=0x0

MCR I prefetch. Assuming the ICache misses, a linefill occurs to line 0.

MCR to CP15 register 9, opcode_2 = 0x1, Victim=Base=0x1

More ICache linefills now occur into lines 1-63.

Example 2-2 shows how you can load a cache line into DCache line 0 and lock it down.

Example 2-2 Load a cache line into DCache line 0 and lock it down

MCR to CP15 register 9, opcode_2 = 0x0, Victim=Base=0x0

Data load (LDR/LDM). Assuming the DCache misses, a linefill occurs to line 0.

MCR to CP15 register 9, opcode_2 = 0x0, Victim=Base=0x1

More DCache linefills now occur into lines 1-63.

ARM920T Datasheet(PDF) 47 Page - ATMEL Corporation