ARM920T datasheet(46/350 Pages) ATMEL

46 / 350 page

Programmer’s Model

2-20

ARM DDI 0151C

Note

These functions invalidate all the unpreserved entries in the TLB. Invalidate TLB single

entry functions invalidate any TLB entry corresponding to the MVA given in Rd,

regardless of its preserved state. See Register 10, TLB lockdown register on page 2-22.

Figure 2-6 shows the MVA format used for operations on single entry TLB lines using

Figure 2-6 Register 8 MVA format

2.3.13

The cache lockdown register allows software to control which cache line in the ICache

or DCache respectively is loaded for a linefill and to prevent lines in the ICache or

DCache from being evicted during a linefill, locking them into the cache.

There is a register for each of the ICache and DCache. The value of opcode_2 determines

which cache register to access:

•

opcode_2 = 0x0

accesses the DCache register

•

opcode_2 = 0x1

accesses the ICache register.

The Opcode_1 and CRm fields should be zero.

Reading CP15 register 9 returns the value of the cache lockdown register, which is the

base pointer for all cache segments.

Invalidate I TLB single entry (using MVA)

MVA

format

MCR p15,0,Rd,c8,c5,1

Invalidate D TLB

SBZ

MCR p15,0,Rd,c8,c6,0

Invalidate D TLB single entry (using MVA)

MVA

format

MCR p15,0,Rd,c8,c6,1

Table 2-17 TLB operations register 8 (continued)

Function

Data

Instruction

10 9

Modified virtual address

SBZ

ARM920T Datasheet(PDF) 46 Page - ATMEL Corporation

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