ARM920T datasheet(48/350 Pages) ATMEL

48 / 350 page

Programmer’s Model

2-22

ARM DDI 0151C

Note

Writing CP15 register 9, with the CRm field set to b0001, updates the current victim

pointer only for the specified segment. Bits [31:26] specify the victim. Bits [7:5] specify

the segment (for a 16KB cache). All other bits should be zero. This encoding is intended

for debug use. You are not recommended to use this encoding.

Figure 2-7 shows the format of bits in register 9.

Figure 2-7 Register 9

Table 2-18 shows the instructions you can use to access the cache lockdown register.

2.3.14

There is a TLB lockdown register for each of the TLBs, the value of opcode_2

determines which TLB register to access:

•

opcode_2 = 0x0

accesses the D TLB register

•

opcode_2 = 0x1

accesses the I TLB register.

Reading CP15 register 10 returns the value of the TLB lockdown counter base register,

the current victim number, and the preserve bit (P bit). Bits [19:1] are unpredictable

when read.

Writing CP15 register 10 updates the TLB lockdown counter base register, the current

victim pointer, and the state of the preserve bit. Bits [19:1] should be zero when written.

26 25

Index

UNP/SBZ

Table 2-18 Accessing the cache lockdown register 9

Function

Data

Instruction

Read DCache lockdown base

Base

MRC p15,0,Rd,c9,c0,0

Write DCache victim and lockdown base

Victim=Base

MCR p15,0,Rd,c9,c0,0

Read ICache lockdown base

Base

MRC p15,0,Rd,c9,c0,1

Write ICache victim and lockdown base

Victim=Base

MCR p15,0,Rd,c9,c0,1

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