ARM920T datasheet(39/350 Pages) ATMEL

39 / 350 page

Programmer’s Model

ARM DDI 0151C

2-13

I bit

ICache enable

0 = ICache disabled.

1 = ICache enabled.

11:10

Reserved

Read = 00.

Write = 00.

R bit

ROM protection

This bit modifies the MMU protection

system. See Domain access control on

page 3-23.

S bit

System protection

This bit modifies the MMU protection

system. See Domain access control on

page 3-23.

B bit

Endianness

0 = Little-endian operation.

1 = Big-endian operation.

6:3

Reserved

Read = 1111.

Write = 1111.

C bit

DCache enable

0 = DCache disabled.

1 = DCache enabled.

A bit

Alignment fault enable

Data address alignment fault checking.

0 = Fault checking disabled.

1 = Fault checking enabled.

M bit

MMU enable

0 = MMU disabled.

1 = MMU enabled.

Table 2-10 Control register 1 bit functions (continued)

bits

Name

Function

Value

ARM920T Datasheet(PDF) 39 Page - ATMEL Corporation

ARM920T Datasheet(HTML) 39 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL