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ARM920T Datasheet(PDF) 45 Page - ATMEL Corporation |
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ARM920T Datasheet(HTML) 45 Page - ATMEL Corporation |
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45 / 350 page  Programmer’s Model ARM DDI 0151C Copyright © 2000, 2001 ARM Limited. All rights reserved. 2-19 The operations that you can carry out on a single cache line identify the line using the data passed in the MCR instruction. The data is interpreted using one of the formats shown in Figure 2-4 or Figure 2-5. Figure 2-4 Register 7 MVA format Figure 2-5 Register 7 index format The use of register 7 is described in Chapter 4 Caches, Write Buffer, and Physical Address TAG (PA TAG) RAM. 2.3.12 Register 8, TLB operations register Register 8 is a write-only register used to manage the Translation Lookaside Buffers (TLBs), the instruction TLB, and the data TLB. Five TLB operations are defined and you can select the function to be performed with the opcode_2 and CRm fields in the MCR instruction used to write CP15 register 8. Writing other opcode_2 or CRm values is unpredictable. Reading from CP15 register 8 is unpredictable. Table 2-17 shows instructions that you can use to perform TLB operations using register 8. 31 54 0 Modified virtual address SBZ 31 26 25 8 7 5 4 0 Index SBZ SBZ Seg Table 2-17 TLB operations register 8 Function Data Instruction Invalidate TLB(s) SBZ MCR p15,0,Rd,c8,c7,0 Invalidate I TLB SBZ MCR p15,0,Rd,c8,c5,0 |
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