HCPL-0870 datasheet(4/28 Pages) HP

4 / 28 page

1-263

Pin Description, Digital Interface IC

Symbol

Description

CCLK

Clock input for the Serial Configuration

Interface (SCI). Serial Configuration

data is clocked in on the rising edge

of CCLK.

CLAT

Latch input for the Serial Configuration

Interface (SCI). The last 8 data bits

clocked in on CDAT by CCLK are

latched into the appropriate

configuration register on the rising

edge of CLAT.

CDAT

Data input for the Serial Configuration

Interface (SCI). Serial configuration

data is clocked in MSB first.

MCLK1

Channel 1 Isolated Modulator clock

input. Input Data on MDAT1 is clocked

in on the rising edge of MCLK1.

MDAT1

Channel 1 Isolated Modulator data

input.

MCLK2

Channel 2 Isolated Modulator clock

input. Input Data on MDAT2 is clocked

in on the rising edge of MCLK2.

MDAT2

Channel 2 Isolated Modulator data

input.

GND

Digital ground.

Symbol

Description

VDD

Supply voltage (4.5 V to 5.5 V).

CHAN

Channel select input. The input level on

CHAN determines which channel of

data is used during the next conversion

cycle. An input low selects channel 1,

a high selects channel 2.

SCLK

Serial clock input. Serial data is clocked

out of SDAT on the falling edge of SCLK.

SDAT

Serial data output. SDAT changes from

high impedance to a logic low output

at the start of a conversion cycle.

SDAT then goes high to indicate that

data is ready to be clocked out. SDAT

returns to a high-impedance state after

all data has been clocked out and CS

has been brought high.

Conversion start input. Conversion

begins on the falling edge of CS. CS

should remain low during the entire

conversion cycle and then be brought

high to conclude the cycle.

THR1

Continuous, programmable-threshold

detection for channel 1 input data. A

high level output on THR1 indicates

that the magnitude of the channel 1

input signal is beyond a user

programmable threshold level between

160 mV and 310 mV. This signal

continuously monitors channel 1

independent of the channel select

(CHAN) signal.

OVR1

High speed continuous over-range

detection for channel 1 input data. A

high level output on OVR1 indicates

that the magnitude of the channel 1

input is beyond full-scale. This signal

continuously monitors channel 1

independent of the CHAN signal.

RESET

Master reset input. A logic high input

for at least 100 ns asynchronously

resets all configuration registers to

their default values and zeroes the

Offset Calibration registers.

HCPL-0870 Datasheet(PDF) 4 Page - Agilent(Hewlett-Packard)

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