HCPL-0870 datasheet(12/28 Pages) HP

12 / 28 page

1-271

Electrical Specifications, Isolated Modulator

Unless otherwise noted, all specifications are at VIN+ = 0 V and VIN- = 0 V, all Typical specifications are at

TA = 25°C and VDD1 = VDD2 = 5 V, and all Minimum and Maximum specifications apply over the following

ranges: TA = -40°C to +85°C, VDD1 = 4.5 to 5.5 V and VDD2 = 4.5 to 5.5 V.

Parameter

Symbol Min. Typ. Max. Units

Test Conditions

Fig.

Note

Average Input Bias Current

IIN

-1.0

µA14

Average Input Resistance

RIN

270

Ω

Input DC Common-Mode

CMRRIN

Rejection Ratio

Output Logic High Voltage

VOH

3.9

4.9

IOUT = -100 µA

Output Logic Low Voltage

VOL

0.3

0.6

IOUT = 1.6 mA

Output Short Circuit Current

|IOSC|10

VOUT = VDD2 or GND2

Input Supply Current

IDD1

9.5

VIN+ = -350 mV

Output Supply Current

IDD2

8.8

Output Clock Frequency

fCLK

MHz

Data Hold Time

tHDDAT

Notes:

14. In accordance with UL1577, for devices with minimum VISO specified at 3750 Vrms, each isolated modulator (optocoupler) is

proof-tested by applying an insulation test voltage greater than 4500 Vrms for one second (leakage current detection limit

II-O <5 µa). This test is performed before the Method b, 100% production test for partial discharge shown in VDE 0884

Insulation Characteristics Table.

15. This is a two-terminal measurement: pins 1-4 are shorted together and pins 5-8 are shorted together.

16. If VIN- (pin 3) is brought above VDD1 - 2 V with respect to GND1 an internal optical-coupling test mode may be activated. This test

mode is not intended for customer use.

17. HP recommends the use of non-chlorinated solder fluxes.

18. Because of the switched-capacitor nature of the isolated modulator, time averaged values are shown.

19. CMRRIN is defined as the ratio of the gain for differential inputs applied between VIN+ and VIN- to the gain for common-mode

inputs applied to both VIN+ and VIN- with respect to input ground GND1.

20. Short-circuit current is the amount of output current generated when either output is shorted to VDD2 or GND2. Use under these

conditions is not recommended.

21. Data hold time is amount of time that the data output MDAT will stay stable following the rising edge of output clock MCLK.

to +350 mV

HCPL-0870 Datasheet(PDF) 12 Page - Agilent(Hewlett-Packard)

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