82374EB datasheet(144/208 Pages) INTEL

144 / 208 page

82374EB82374SB

71 Arbitration Priority

At the top level of the arbiter the ESC uses a three way rotating priority arbitration method On a fully loaded

bus the order in which the devices are granted bus access is independent of the order in which they assert a

bus request since devices are serviced based on their position in the rotation The arbitration scheme assures

that DMA channels and EISA masters are able to access the bus with minimal latency

The PCEB and EISA Masters share one of the slots in the three way rotating priority scheme This sharing is a

two way rotation between the CPU and EISA Masters as a group In this arbitration scheme the PCEB acts on

behalf of the CPU and all other PCI masters

EISA Masters have a rotating priority structure which can handle up to eight master requests

The next position in the top level arbiter is occupied by the DMA The DMA’s DREQ lines can be placed in

either fixed or rotating priority The default mode is fixed and by programming the DMA Command registers

the priority can be modified to rotating priority mode

72 Preemption

An EISA compatible arbiter ensures that minimum latencies are observed for both EISA DMA devices and

EISA Masters

721 PCEB EISA BUS ACQUISITION AND PCEB PREEMPTION

EISA bus arbitration is intended to be optimized for CPU access the EISA bus Since the CPU accesses to the

EISA Bus through the PCEB the PCEB is assumed to be the default owner of the EISA bus The arbitration

interface between the PCEB and the ESC is implemented as a HOLDHLDA (EISAHOLD EISAHLDA) pair

If a PCI cycle requires access to the EISA Bus while EISAHLDA signal is asserted (EISA Bus busy) the PCI

cycle is retried and the PCEB requests the EISA bus by asserting PEREQ

The ESC after sampling PER-

asserted preempts the current owner of the EISA Bus The ESC grants the EISA Bus by negating

EISAHOLD signal

The ESC asserts EISAHOLD to the PCEB when the ESC needs to acquire the ownership of the EISA bus

While EISAHOLD is asserted the arbitration process is dynamic and may change (ie the ESC is still accept-

ing EISA Bus requests) When the PCEB returns EISAHLDA the arbiter freezes the arbitration process and

determine the winner If the new winner is an EISA Master or DMA channel the ESC will assert NMFLUSH

The ESC tri-states the NMFLUSH

output driver on the following clock The PCEB holds NMFLUSH

assert-

ed until all buffers are flushed After all buffers are flushed the PCEB negates NMFLUSH

and then tri-state

the output buffer After sampling NMFLUSH

negated the ESC resumes driving NMFLUSH

on the next PCI

clock This way the ESC does not assert MACK

or DACK

until the PCEB acknowledges that all line buffers

have been flushed

144

82374EB Datasheet(PDF) 144 Page - Intel Corporation

82374EB Datasheet(HTML) 144 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL