82374EB datasheet(142/208 Pages) INTEL

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82374EB82374SB

69 Terminal CountEOP Summary

Table 19 is a summary of the events that happen as a result of a terminal count or external EOP when running

DMA in various modes

Table 19 Terminal CountEOP Summary Table

Conditions

AUTOINIT

Yes

Event

Word Counter Expired

Yes

EOP Input

Asserted

Result

Status TC

set

Mask

set

SW Request

clr

Current Register

load

NOTES

1 loadeLoad Current From Base

2 ‘‘-’’eNo Change

3 XeDon’t Care

4 clreClear

610 Buffer Chaining

The buffer chaining mode of a channel is useful for transferring data from a peripheral to several different

areas of memory within one transfer operation (from the DMA device’s viewpoint) This is accomplished by

causing the DMA to interrupt the CPU for more programming information while the previously programmed

transfer is still in progress Upon completion of the previous transfer the DMA controller will then load the new

transfer information automatically In this way the entire transfer can be completed without interrupting the

operation of the DMA device This mode is most useful for DMA single-cycle or demand modes where the

transfer process allows time for the CPU to execute the interrupt routine

The buffer chaining mode of a channel may be entered by programming the address and count of a transfer as

usual After the initial address and count is programmed the Base registers are selected via the Chaining

Mode register Chaining Mode Enabled bit The address and count for the second transfer and both the

Chaining Mode Enabled and the Program Complete bit of the Chaining Mode register should be programmed

at this point before starting the DMA process When during the DMA process the Current Buffer is expired

the Base address Page and Count registers will be transferred to the Current registers and a signal that the

buffer has been expired is sent to the programming master

This signal will be an IRQ13 if the master is the CPU or a TC if the programming master is an EISA Master

device The type of programming master is indicated in the DMA’s Chaining Mode Register bit 4 If the CPU is

the programming master for the Channel TC will be generated only if the Current buffer expires and there is no

Next Buffer stored in the Base registers

142

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