82374EB datasheet(140/208 Pages) INTEL

140 / 208 page

82374EB82374SB

The beginning and end of the ring buffer area is defined in the Base Address register and the Base Address

the ring buffer When the DMA reaches the end of the ring buffer indicating the byte count has expired the

DMA controller (if so programmed) will autoinitialize Upon autoinitialization the Current Address register will

be restored from the Base Address register taking the process back to the start of the ring buffer The DMA

will then be available to begin depositing the incoming bytes in the ring buffers sequential locations providing

that the CPU has read the data that was previously placed in those locations The DMA determines that the

CPU has read certain data by the value that the CPU writes into the Stop register

Once the data of a frame is read by the CPU the memory location it occupies becomes available for other

incoming frames The Stop register prevents the DMA from over writing data that has not yet been read by the

CPU After the CPU has read a frame from memory it will update the Stop register to point to the location that

was last read The DMA will not deposit data into any location beyond that pointed to by the Stop register The

last address transferred before the channel is masked is the first address that matches the Stop register

For example if the stop register e 00001Ch the last three transfers are shown in Table 18

Table 18 Stop Register Functionality Example

By Bytes

By Words

Increment

XX00001Ah

XX000018h

XX00001Bh

XX00001Ah

XX00001Ch

Decrement

XX000021h

XX000023h

XX000020h

XX000021h

XX00001Fh

NOTE

The Stop registers store values to compare against LA 232 only so the size of the ring buffer is limited to 16 MBytes

675 BUFFER CHAINING MODE AND STATUS REGISTERS

The Chaining Mode registers are used to implement the buffer chaining mode of a channel The buffer

chaining mode is useful when transferring data from a peripheral to several different areas of memory with one

continuous transfer operation Four registers are used to implement this function the Chaining Mode register

the Chaining Mode Status Register the Channel Interrupt Status register and the Chain Buffer Expiration

Control register

The Chaining Mode register controls the buffer chaining initialization Buffer chaining mode can be enabled or

disabled A Chaining Mode bit is used to indicate if Base register programming is complete and chaining can

begin or to hold off chaining because the Base registers still need programming Another bit dictates the

buffer expiration response by indicating whether an IRQ13 or EOP should be issued when the buffer needs

reprogramming The Chaining Mode Status Register indicates whether each channel’s chaining mode is en-

abled or disabled

The Channel Interrupt Status Register indicates the channel source of a DMA chaining interrupt on IRQ13

The CPU can read this register to determine which channel asserted IRQ13 following a buffer expiration The

Chain Buffer Expiration Control Register is a read only register that reflects the outcome after the expiration of

a chain buffer If a channel bit is set to 0 IRQ13 will be activated following the buffer expiration If a channel bit

is set to 1 EOP will be asserted following the buffer expiration

140

82374EB Datasheet(PDF) 140 Page - Intel Corporation

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