82374EB datasheet(136/208 Pages) INTEL

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82374EB82374SB

Fixed Priority

The initial fixed priority structure is as follows

High priority

Low priority

(0 1 2 3) 5 6 7

The fixed priority ordering is 0 1 2 3 5 6 and 7 In this scheme Channel 0 has the highest priority and

Channel 7 has the lowest priority Channels 30 of DMA-1 assume the priority position of Channel 4 in DMA-

2 thus taking priority over Channels 5 6 and 7

Rotating Priority

Rotation allows for ‘‘fairness’’ in priority resolution The priority chain rotates so that the last channel serviced

is assigned the lowest priority in the Channel group (0-3 5-7) Channels 0-3 rotate as a group of 4 They are

always placed between Channel 5 and Channel 7 in the priority list Channel 5-7 rotate as part of a group of 4

That is Channels (5-7) form the first three partners in the rotation while Channel group (0-3) comprises the

fourth position in the arbitration Table 15 demonstrates rotation priority

Table 15 Rotating Priority Example

Programmed Mode

Action

Priority

High

Low

Group (0-3) is in rotation mode

1) Initial Setting

(0 1 2 3) 5 6 7

Group (4-7) is in fixed mode

2) After servicing channel 2

(3 0 1 2) 5 6 7

3) After servicing channel 3

(0 1 2 3) 5 6 7

Group (0-3) in rotation mode

1) Initial Setting

(0 1 2 3) 5 6 7

Group (4-7) is in rotation mode

2) After servicing channel 0

5 6 7 (1 2 3 0)

3) After servicing channel 5

6 7 (1 2 3 0) 5

(note that the first servicing of

4) After servicing channel 6

7 (1 2 3 0) 5 6

channel 0 caused double rotation)

5) After servicing channel 7

(1 2 3 0) 5 6 7

66 Scatter-Gather Functional Description

Scatter-Gather provides the capability of transferring multiple buffers between memory and IO without CPU

intervention In Scatter-Gather the DMA can read the memory address and word count from an array of buffer

descriptors called the Scatter-Gather Descriptor (SGD) Table This allows the DMA to sustain DMA transfers

until all buffers in the Scatter-Gather Descriptor Table are transferred

The Scatter-Gather Command register and Scatter-Gather Status register are used to control the operational

aspect of Scatter-Gather transfers (see Section 32 for details of these registers) The Scatter-Gather Descrip-

tor Next Link register holds the address of the next buffer descriptor in the Scatter-Gather Descriptor Table

The next buffer descriptor is fetched from the Scatter-Gather Descriptor Table by a DMA read transfer

DACK

will not be asserted for this transfer because the IO device is the DMA itself and the DACK is internal

to the ESC The ESC will assert IOWC

for these bus cycles like any other DMA transfer The ESC will behave

as an 8-bit IO slave and will run type ‘‘B’’ timings for a Scatter-Gather buffer descriptor transfer EOP will be

asserted at the end of the transfer

136

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