82374EB datasheet(138/208 Pages) INTEL

138 / 208 page

82374EB82374SB

290476 – 79

Figure 16 Link List Example

67 Register Functionality

See Section 32 for detailed information on register programming bit definitions and default valuesfunctions

after a reset

DMA Channel 4 is used to cascade the two DMA controllers together and should not be programmed for any

mode other than cascade The Mode register for Channel 4 will default to cascade mode Special attention

should also be take when programming the Command and Mask registers as related to Channel 4 (refer to the

Command and Mask register descriptions Section 32)

671 ADDRESS COMPATIBILITY MODE

Whenever the DMA is operating in Address Compatibility mode the addresses do not increment or decrement

through the High and Low Page registers and the high page register is set to 00h This is compatible with the

82C37 and Low Page register implementation used in the PC AT This mode is set when any of the lower three

address bytes of a channel are programmed If the upper byte of a channel’s address is programmed last the

channel will go into Extended Address Mode In this mode the high byte may be any value and the address

will increment or decrement through the entire 32-bit address

138

82374EB Datasheet(PDF) 138 Page - Intel Corporation