82374EB datasheet(139/208 Pages) INTEL

139 / 208 page

82374EB82374SB

After reset is negated all channels will be set to Address Compatibility Mode The DMA Master Clear com-

mand will also reset the proper channels to Address Compatibility Mode The Address Compatibility Mode bits

are stored on a per channel basis

672 SUMMARY OF THE DMA TRANSFER SIZES

Table 16 lists each of the DMA device transfer sizes The column labeled ‘‘Word Count Register’’ indicates

that the register contents represent either the number of bytes to transfer or the number of 16-bit words to

transfer The column labeled ‘‘Current Address Register IncrementDecrement’’ indicates the number added

to or taken from the Current Address register after each DMA transfer cycle The Mode Register determines if

the Current Address register will be incremented or decremented

Table 16 DMA Transfer Size

DMA Device Date Size And Word Count

Word Count

Current Address

IncrementDecrement

8-bit IO Count By Bytes

Bytes

16-bit IO Count By Words (Address Shifted)

Words

16-bit IO Count By Bytes

Bytes

32-bit IO Count By Bytes

Bytes

673 ADDRESS SHIFTING WHEN PROGRAMMED FOR 16-BIT IO COUNT BY WORDS

To maintain compatibility with the implementation of the DMA in the PCAT which used the 82C37 the DMA

will shift the addresses when the Extended Mode register is programmed for or defaulted to transfers tofrom

a 16-bit device count673-by-words Note that the least significant bit of the Low Page register is dropped in

16-bit shifted mode When programming the Current Address register while the DMA channel is in this mode

the Current Address must be programmed to an even address with the address value shifted right by one bit

The address shifting is as shown in Table 17

Table 17 Address Shifting in 16-Bit IO DMA Transfers

Output

8-Bit IO

16-Bit IO

32-Bit IO

Address

Programmed

Address

Address (Shifted)

Address (No Shift)

‘‘0’’

161

A 161

A 150

A 1601

A 3117

NOTE

The least significant bit of the Low Register is dropped in 16-bit shifted mode

674 STOP REGISTERS (RING BUFFER DATA STRUCTURE)

To support a common data communication data structure (the ring buffer) a set of DMA registers have been

provided These registers are called Stop registers Each channel has 22-bits of register location associated

with it The 22-bits are distributed between three different registers (one 8-bit and two 8-bit) The Stop registers

can be enabled or disabled by writing to the channel’s corresponding Extended Mode register

The ring buffer data structure reserves a fixed portion of memory on Dword boundaries to be used for a DMA

channel Consecutively received frames or other data structures are stored sequentially within the boundaries

of the ring buffer memory

139

82374EB Datasheet(PDF) 139 Page - Intel Corporation

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