82374EB datasheet(135/208 Pages) INTEL

135 / 208 page

82374EB82374SB

644 TYPE ‘‘C’’ (BURST) TIMING

Type ‘‘C’’ (burst) timing is provided for EISA DMA devices The DMA slave device needs to monitor EXRDY

and IORC

or IOWC

signals to determine when to change the data (on writes) or sample the data (on

reads) This timing will allow up to 33 MBytes per second transfer rate with a 32-bit DMA device and 32-bit

memory Note that 8- or 16-bit DMA devices are supported (through the programmable DMA address incre-

ment) and that they use the ‘‘byte lanes’’ natural to their size for the data transfer As with all bursts the

system will revert to two BCLK cycles if the memory does not support burst When a DMA burst cycle

accesses non-burst memory and the DMA cycle crosses a page boundary into burstable memory the ESC will

continue performing standard (non-burst) cycles This will not cause a problem since the data is transferred

correctly

290476 – 77

Figure 14 Type ‘‘C’’ (Burst) DMA Read Transfers (1 BCLK)

65 Channel Priority

For priority resolution the DMA consists of two logical channel groups-channels 0-3 and channels 4-6 Each

group may be in either Fixed or Rotate mode as determined by the Command register

For arbitration purposes the source of the DMA request is transparent DMA IO slaves normally assert their

DREQ line to arbitrate for DMA service However a software request for DMA service can be presented

through each channel’s DMA Request register A software request is subject to the same prioritization as any

hardware request Please see the detailed register description in Section 30 for Request Register program-

ming information

135

82374EB Datasheet(PDF) 135 Page - Intel Corporation