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82374EB Datasheet(PDF) 133 Page - Intel Corporation |
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82374EB Datasheet(HTML) 133 Page - Intel Corporation |
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133 / 208 page  82374EB82374SB 642 TYPE ‘‘A’’ TIMING Type ‘‘A’’ timing is provided to allow shorter cycles to EISA memory (Note Main memory behaves like EISA memory because the PCEB has an EISA slave interface) Type ‘‘A’’ timing runs at 7 BCLKs (840 nssingle cycle) and 6 BCLKs (720 nscycle) during the repeated portion of a Block or Demand mode transfer Type ‘‘A’’ timing varies from compatible timing primarily in shortening the memory operation to the minimum allowed by system memory The IO portion of the cycle (data setup on write IO read access time) is the same as with compatible cycles The actual active command time is shorter but it is expected that the DMA devices which provide the data access time or write data setup time should not require excess IORC or IOWC command active time Because of this most DMA devices should be able to use type ‘‘A’’ timing 290476 – 75 Figure 12 Type ‘‘A’’ DMA Read Transfers (6 BCLKS) 133 |
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