82374EB datasheet(131/208 Pages) INTEL

131 / 208 page

82374EB82374SB

624 CASCADE MODE

This mode is used to cascade more than one DMA controller together for simple system DMA requests for the

additional device propagate through the priority network circuitry of the preceding device The priority chain is

preserved and the new device must wait for its turn to acknowledge requests Within the ESC architecture

Channel 0 of DMA Controller two (DMA-2 Ch 4) is used to cascade DMA Controller one (DMA-1) to provide a

total of seven DMA channels Channel 0 on DMA-2 (labeled Ch 4 overall) connects the second half of the

DMA system This channel is not available for any other purpose

In Cascade Mode the DMA Controller will respond to DREQ with DACK but the ESC will not drive the bus

Cascade mode is also used to allow direct access of the system by 16-bit bus masters These devices use the

DREQ and DACK signals to arbitrate for the system bus and then they drive the address and command lines

to control the bus The ISA master asserts its ISA master request line (DREQx) to the DMA internal arbiter If

the ISA master wins the arbitration the ESC responds with an ISA Master Acknowledge (DACKx) signal active

Upon sampling the DACKx line active the ISA Master asserts MASTER16

signal and takes control of the

EISA bus The ISA Master has control of the EISA Bus and the ISA Master may run cycles until it negates the

MASTER16

signal

63 DMA Transfer Types

Each of the three active transfer modes (Single Block or Demand) can perform three different types of

transfers These transfers are Read Write and Verify

Write Transfer

Write transfers move data from an EISAISA IO device to memory located on EISAISA Bus or PCI Bus The

DMA indicates the transfer type to the EISA bus controller The bus controller will activate IORC

and the

appropriate EISA control signals (MIO

and WR ) to indicate a memory write

Read Transfer

Read transfers move data from EISAISA or PCI memory to an EISAISA IO device The DMA indicates the

transfer type to the EISA bus controller The bus controller will activate IOWC

and the appropriate EISA

control signals (MIO

and WR ) to indicate a memory read

Verify Transfer

Verify transfers are pseudo transfers The DMA controller operates as in Read or Write transfers generating

addresses and producing TC etc However the ESC does not assert the memory and IO control signals

Only the DACK signals are asserted Internally the DMA controller will count BCLKs so that the DACK signals

have a defined pulse width This pulse width is nine BCLKs long If Verify transfers are repeated during Block

or Demand DMA requests each additional pseudo transfer will add eight BCLKs The DACK signals will not be

toggled for repeated transfers

64 DMA Timing

The ESC DMA provides four transfer timings In addition to the compatible timings the ESC DMA provides

Type ‘‘A’’ Type ‘‘B’’ and Type ‘‘C’’ (burst) timings for IO slave devices capable of running at faster speeds

131

82374EB Datasheet(PDF) 131 Page - Intel Corporation

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