82374EB datasheet(128/208 Pages) INTEL

128 / 208 page

82374EB82374SB

592 MACKX

GENERATION

The ESC generates the EISA Master Acknowledge signals if the ESC is configured for to directly support 4

masters through Mode Select register bit 10 In this case the ESC generates MACKx s for Master 0-3 If the

ESC is programmed to support more than 4 EISA slots the ESC will generate Encoded (E)MACKx s Discrete

logic like a F138 is required to generate the MACKx s for the Masters

Table 14 Encoded MACK

(EMACKx ) Generation

EMACK 41

MACK7

MACK6

MACK5

MACK4

MACK3

MACK2

MACK1

MACK0

0000

0001

0010

0011

0100

0101

0110

0111

1111

NOTE

EMACK 41 combinations 1000 – 1110 are Reserved

60 DMA CONTROLLER

61 DMA Controller Overview

The DMA circuitry incorporates the functionality of two 82C37 DMA controllers with seven independently

programmable channels (Channels 0-3 and Channels 5-7) DMA Channel 4 is used to cascade the two

controllers together and will default to cascade mode in the Mode register In addition to accepting requests

from DMA slaves the DMA also responds to requests that are initiated by software Software may initiate a

DMA service request by setting any DMA Channel Request register bit to a 1 The DMA controller for Channels

0-3 is referred to as ‘‘DMA-1’’ and the controller for Channels 4-7 is ‘‘DMA-2’’

128

82374EB Datasheet(PDF) 128 Page - Intel Corporation