82374EB datasheet(124/208 Pages) INTEL

124 / 208 page

82374EB82374SB

Table 10 Number of BCLKs for ISA Master Cycles

Cycle Type

Bus

No Wait State

Standard CHRDYe1

One Wait State

Size

NOWS

CHRDYe0

Number of BCLKs

ReadWrite

Memory

ReadWrite

Memory

4 5

IO ReadWrite

4 5

DMA Compatible

816

DMA Type A(1)

816

DMA Type B(1)

816

DMA Type C(2)

816

NOTES

1 If ISA memory responds the ESC will extend the cycle by 1 BCLK

2 If ISA memory responds the ESC will use DMA Type B read cycle timing

55 Mis-Match Cycles

Data size translation is performed by the ESC for all mis-matched cycles A mis-matched cycle is defined as a

cycle in which the bus master and bus slave do not have equal data bus sizes (eg a 32-bit EISA master

accessing a 16-bit ISA slave) The data size translation is performed in conjunction with the PCEB The ESC

generates the appropriate cycles and data steering control signals for mis-matched cycles The PCEB uses

the data steering control signals from the ESC to latch and redirect the data to the appropriate byte lanes The

ESC will perform one or more of the following operations depending on the master and slave type transfer

direction and the number of byte enables active

Table 11 Mis-Match Master Slave Combinations

Master Type

Cycle Type

Slave Type

32-Bit

16-Bit

8-Bit

EISA

ISA

EISAISA

downshift

32-bit EISA with 16-bit

Burst

Standard

match

Mis-Match

32-bit EISA

Burst

Standard

match

Mis-Match

16-bit EISA

Burst

Standard

Mis-Match

match

Mis-Match

NOTE

na Not Applicable The cycle will never occur

124

82374EB Datasheet(PDF) 124 Page - Intel Corporation

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