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82374EB Datasheet(PDF) 121 Page - Intel Corporation |
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82374EB Datasheet(HTML) 121 Page - Intel Corporation |
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121 / 208 page  82374EB82374SB 54 ISA Master Cycles ISA cycles are initiated on the ISA bus by an ISA master These cycles are accesses to the following system resources EISA slaves devices (including PCEB for PCI agents) ISA slave devices ESC internal registers (8-bit EISA Slave) The ISA Master initiates such a cycle by asserting the DREQx line to the ESC The ESC after performing the necessary arbitration asserts the corresponding DACKx line Upon receiving an acknowledge from the ESC the ISA master asserts the MASTER16 signal line to indicate that it has control of the ISA bus and a cycle on the ISA bus will take place The ESC translates the ISA address signals SBHE SA1 and SA0 to EISA byte enables BE 30 541 ISA MASTER TO 32-16-BIT EISA SLAVE An EISA slave will decode the address to determine if it has been selected In response to a positive decode the EISA slave will assert EX32 or EX16 The ESC samples these signals to determine if an EISA Slave has been selected If these signals are asserted the ESC will perform ISA to EISA cycle translation by driving the EISA control signals The ISA Master asserts one of the ISA command signals MRDC MWTC IORC or IOWC depending on whether or not the access is to a memory an IO device or an IO register The ISA command signals will remain active until the end of the cycle The ESC will generate the EISA translation by generating the EISA control signals START CMD MIO and WR The EISA slave can add wait states by negating EXRDY The ESC samples EXRDY and translates it into CHRDY The ESC will also generate the control signals to steer the data to the appropriate byte lanes for mis- matched cycles 542 ISA MASTER TO 16-BIT ISA SLAVE An ISA Master initiates cycles to ISA slave devices These cycles are either memory readwrite or IO read write The ISA bus Master is assumed to be 16-bit device and it can access either 8- or 16-bit slave devices that reside on the ISA bus A 16-bit ISA slave device will respond to a valid address by asserting M16 for memory cycles and IO16 for IO cycles The ESC is inactive during ISA Master cycles where either M16 or IO16 is sampled asserted 121 |
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