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82374EB Datasheet(PDF) 117 Page - Intel Corporation

Part # 82374EB
Description  SYSTEM COMPONENT (ESC)
PDF  208 Pages
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Manufacturer  INTEL [Intel Corporation]
Direct Link  http://www.intel.com
Logo INTEL - Intel Corporation

82374EB Datasheet(HTML) 117 Page - Intel Corporation

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82374EB82374SB
290476 – 66
Figure 3 BCLK Stretching
53 EISA Master Cycles
EISA Master cycles are initiated on the EISA bus by an EISA Master (including PCEB for PCI agents) These
cycles are accesses to the following resources
 EISA slaves devices (including PCEB for PCI agents)
 ISA slave devices
 ESC internal registers (8-bit EISA Slave)
An EISA master gains control of the bus by asserting MREQx
(PEREQ
in case of PCEB) to the ESC The
ESC after performing the necessary arbitration asserts the corresponding MACKn
(negates EISAHOLD in
case of the PCEB) Refer to Section 70 for arbitration protocol
In response to receiving the acknowledge signal the EISA Master starts the cycle by driving the bus with
LA 3102
BE 30
WR and MIO The EISA Master then asserts START
to indicate the beginning of the
current cycle A 16-bit EISA Master will also assert MASTER16
at this time The ESC generates SBEH
S1
and S0 signals from the BE 30
signals
531 EISA MASTER TO 32-BIT EISA SLAVE
An EISA slave after decoding it’s address asserts EX32
or EX16
The EISA master and the ESC use these
signals to determine the EISA slave data size The 32-bit or 16-bit EISA master continues with the cycles if
EX32
or EX16
is asserted respectively The ESC acts as a central resources for the EISA master and
generates CMD
for the cycles The ESC asserts CMD
on the same BCLK edge that START
is negated
The ESC monitors the EXRDY signal on the EISA bus to determine when to negate the CMD
An EISA Slave
can extend the cycle by negating EXRDY EISA specification require that EXRDY not be held negated for more
than 25 ms A burstable EISA slave asserts SLBURST
signal the same time the slave decodes it’s address
The EISA master will sample SLBURST
and assert MSBURST
if it is capable of bursting The ESC keeps
the CMD
asserted during a burst EISA transfer The ESC deasserts CMD
to indicate the end of the burst
transfer after the EISA master deasserts MSBURST
117



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