82374EB datasheet(116/208 Pages) INTEL

116 / 208 page

82374EB82374SB

Generates Data Swap Buffer Control

The EISA controller generates the control signals for the data bus swap control (assemblydisassembly) and

swapping process to support data size mismatches of the devices on the EISA and ISA buses The actual data

steering and swapping is performed by the PCEB

Generate Wait States

The wait state generator is responsible for generating the wait states based on the sampling of the EXRDY

CHRDY NOWS

and the default wait states The default wait state depends on the cycle type

52 Clock Generation

The ESC is generates the EISA Bus clock The ESC uses a divider circuit to generate the EISA Bus clock The

ESC supports PCI bus frequencies between 25 MHz and 33 MHz The PCI clock is divided by 3 or 4 by the

clock generation logic in the ESC The EISA Clock Divisor register bits 20 select the divide value

The ESC provides the EISA Bus clock as the BCLKOUT output Although the ESC is capable of driving 240 pF

load on the BCLKOUT pin it is recommended that this signal be buffered to protect the EISA BCLK signal

The ESC EISA control logic and EISA interface is synchronous to the BCLK input A maximum delay of 15 ns is

allowed between the BCLKOUT output and the BCLK input for proper device functionality

Table 9 PCICLK and BCLK Frequency Relationship

PCICLK

DIVISOR

BCLK

(MHz)

(Programmable)

(MHz)

833

333

833

NOTE

The ESC wakes up after reset with a default divisor value of 4

521 CLOCK STRETCHING

The ESC is capable of stretching EISA Bus clock (BCLKOUT) for PCEB generated EISA cycles The ESC

stretches the EISA Bus clock (BCLKOUT) in order to minimize the synchronization penalty between PCI clock

and EISA clock for accesses to EISA Bus by PCI agents The PCEB initiates an EISA cycle by asserting

START

synchronous to PCICLK The ESC ensures the START

minimum pulse width is met by stretching

the EISA Bus clock low time

The ESC samples START

on every PCICLK when the PCEB has the EISA Bus After sampling START

asserted the ESC delays the rising edge of BCLKOUT until the START

has met the 115 ns minimum pulse

width specification

116

82374EB Datasheet(PDF) 116 Page - Intel Corporation

82374EB Datasheet(HTML) 116 Page - Intel Corporation

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