82374EB datasheet(112/208 Pages) INTEL

112 / 208 page

82374EB82374SB

Table 5 Configuration Register Index Address

(Continued)

Configuration

Abbreviation

Offset

6Eh

GPCSM2

General Purpose Chip Select 2 Mask

6Fh

GPXBC

General Purpose Peripheral X-Bus Control

70h

PACC

PICAPIC Configuration Control

71 – 87h

Reserved

88h

TSTC

Test Control

89 – 9Fh

Reserved

A0h

SMICNTL

SMI Control

A2-A3h

SMIEN

SMI Enable

A4-A7h

SEE

System Event Enable

A8h

FTMR

Fast Off Timer

A9h

Reserved

AA-ABh

SMIREQ

SMI Request

ACh

CTLTMRL

Clock Scaling STPCLK

Low Timer

ADh

Reserved

AEh

CTLTMRH

Clock Scaling STPCLK

High Timer

AF-FFh

Reserved

44 X-Bus Peripherals

The ESC generates chip selects for certain functions that typically reside on the X-Bus The ESC asserts the

chip selects combinatorially from the LA addresses The ESC generates chip select signals for the Keyboard

Controller Floppy Disk Controller IDE Parallel Port Serial Port and General Purpose peripherals The ESC

also generates read and write strobes for Real Time Clock and Configuration RAM The read and write strobes

are a function of LA addresses the ISA read and write strobes (IORC

and IOWC ) and BCLK All of the

peripherals supported by the ESC are at fixed IO addresses with the exception of the general purpose

peripherals The ESC support for these peripherals can be enabled or disabled through configuration registers

Peripheral Chip Select A and Peripheral Chip Select B The general purpose peripherals are mapped to IO

addresses by programming a set of configuration registers General Purpose Chip Select x Base Low Address

112

82374EB Datasheet(PDF) 112 Page - Intel Corporation

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