82374EB datasheet(114/208 Pages) INTEL

114 / 208 page

82374EB82374SB

Table 6 X-Bus Chip Selects Decode

(Continued)

Address

(Hex)

Address (Bit)

Name

Chip Select

FEDC

BA98

7654

3210

03F7h

0000

0011

0111

IDE Controller

1-Primary

(IDECS1 )

ECS 20 e100

03F7h

0000

0011

0111

Primary

Controller-

Floppy Disk

FDCCS

03FFh

03F8h –

0000

0011

1111

1000

COM 1

Serial Port

(COMxCS )

ECS 20 e00x

08FFh

0800h –

0000

1000

xxxx

RAM

Configuration

CRAMRD

CRAMWR

45 IO APIC Registers

The APIC’s registers are indirectly address through two 32 bit registers located in the CPU’s memory space

the IO Register Select (IOREGSEL) and IO Window (IOWIN) Registers (Table 7) These registers can be

relocated via the APIC Base Address Relocation Register and are aligned on 128 bit boundaries

To access an IO APIC register the IOREGSEL Register is written with the address of the intended APIC

becomes a 32-bit window pointing to the register selected by the IOREGSEL Register Note that for each

redirection table register there are two offset addresses (eg

address offset 10h selects IOREDTBL0

bits 310 and 11h selects IOREDTBL0 bits 6332

Table 7 Memory Address For Accessing APIC Registers

Memory

Mnemonic

Access

Address

FEC0 x000h

IOREGSEL

IO Register Select

(82374EB)

FEC0 xy00h

(82374SB)

FEC0 x010h

IOWIN

IO Window

(82374EB)

FEC0 xy10h

(82374SB)

NOTE

xy are determined by the x and y (82374SB only) fields in the APIC Base Address Relocation Register Range for x e 0-Fh

and the range for y e 048Ch

114

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