82374EB datasheet(115/208 Pages) INTEL

115 / 208 page

82374EB82374SB

Table 8 IO APIC Registers

Memory

Mnemonic

Access

Address

00h

IOAPICID

IO APIC ID

01h

IOAPICVER

IO APIC Version

02h

IOAPICARB

IO APIC Arbitration ID

10-2Fh

IOREDTBL 015

Redirection Table (Entries 0-15) (63 bits each)

NOTE

Address Offset is determined by IO Register Select Bits 70

50 EISA CONTROLLER FUNCTIONAL DESCRIPTION

51 Overview

The EISA controller in the ESC provides MasterSlave EISA interface function for the ESC internal resources

In addition the ESC acts as an EISA central resource for the system As a system central resource the EISA

controller is responsible for generating the translation control signals necessary for bus-to-bus transfers

These translation includes transfer between devices on EISA Bus and ISA Bus and transfers between different

size master device and slave device The EISA controller generates the control signals for EISA Data Swap

Buffers integrated in the PCEB The ESC EISA interface generates cycles for DMA transfers and refresh The

ESC internal registers are accessed through the EISA slave interface The ESC is responsible for supporting

the following

Service EISA Master cycles to

EISA slaves devices

ISA slave devices

ESC internal registers

Service ISA Master cycles to

EISA slave devices

ISA (mis-matched) slave devices

ESC internal registers

Service DMA cycles

Fromto DMA slave on the EISA bus tofrom memory on the EISAISA bus

Fromto DMA slave on the ISA bus tofrom memory on the EISAISA bus

Fromto DMA slave on the EISAISA bus tofrom memory on the PCI bus

Service Refresh Cycles

The EISA controller will service the refresh cycle by generating the appropriate address and command signals

These cycles are initiated by either the ESC internal refresh logic or by an external ISA-Bus Master

115

82374EB Datasheet(PDF) 115 Page - Intel Corporation

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