82374EB datasheet(146/208 Pages) INTEL

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82374EB82374SB

722 EISA MASTER PREEMPTION

EISA specification requires that EISA Masters must release the bus within 64 BCLKs (8 ms) after the ESC

negates MACKx

If the bus master attempts to start a new bus cycle after this timeout period a bus timeout

(NMI) is generated and the RSTDRV is asserted to reset the offending bus master

723 DMA PREEMPTION

A DMA slave device that is not programmed for compatible timing is preempted from the EISA Bus by another

device that requests use of the bus This will occur regardless of the priority of the pending request For DMA

devices not using compatible timing mode the DMA controller stops the DMA transfer and releases the bus

within 32 BCLK (4 ms) of a preemption request Upon the expiration of the 4 ms timer the DACK is negated

after the current DMA cycle has completed The EISA Bus then arbitrated for and granted to the highest

priority requester This feature allows flexibility in programming the DMA for long transfer sequences in a

performance timing mode while guaranteeing that vital system services such as Refresh are allowed access to

the expansion bus

The 4 ms timer is not used in compatible timing mode It is only used for DMA channels programmed for Type

‘‘A’’ Type ‘‘B’’ or Type ‘‘C’’ (Burst) timing The 4 ms timer is also not used for 16-bit ISA masters cascaded

through the DMA DREQ lines

If the DMA channel that was preempted by the 4 ms timer is operating in Block mode an internal bit will be set

so that the channel will be arbitrated for again independent of the state of DREQ

73 Slave Timeouts

A slave which does not release EXRDY or CHRDY can cause the CMD

active time to exceed 256 BCLKs

(32 ms) The ESC does not monitor EXRDY or CHRDY for this timeout Typically this function is provided in a

system through a third party add-in card The add-in cards which monitor EXRDY or CHRDY assert IOCHK

signal when the 256 BCLK count expires The ESC in response asserts NMI

The only way that a 16-bit ISA Master can be preempted from the EISA bus is if it exceeds the 256 BCLK

(32 ms) limit on CMD

active

74 Arbitration During Non-Maskable Interrupts

If a non-maskable interrupt (NMI) is pending at the PCEB and the PCEB is requesting the bus the DMA and

EISA Masters will be bypassed each time they come up for rotation This gives the PCEB the EISA Bus

bandwidth on behalf of the CPU to process the interrupt as fast as possible

80 INTERVAL TIMERS

The ESC contains five countertimers that are equivalent to those found in the 82C54 programmable interval

timer The five counters are contained in two separate ESC timer units referred to as Timer-1 and Timer-2

The ESC uses the Timers to implement key EISA system functions Timer-1 contains three counters and

Timer-2 contains two counters EISA systems do not use the middle counter on Timer-2

Interval Timer 1 Counter 0 is connected to the interrupt controller IRQ0 and provides a system timer interrupt

for a time-of-day diskette time-out or other system timing functions Counter 1 generates a refresh-request

signal and Counter 2 generates the tone for the speaker

146

82374EB Datasheet(PDF) 146 Page - Intel Corporation

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