82374EB datasheet(147/208 Pages) INTEL

147 / 208 page

82374EB82374SB

Interval Timer 2 Counter 0 implements a fail safe timer Counter 0 generates NMI at regular intervals thus

preventing the system from locking up Counter 1 is not used Counter 2 is used to slow down the CPU by

means of pulse-width modulation The output of Timer 2 Counter 2 is tied to the SLOWH

signal

Table 20 Interval Timer Functions

Function

Counter 0 System Timer

Counter 0 Fail-Safe Timer

Gate

Always On

Clock In

1193 MHz(OSC12)

0298 MHz(OSC48)

Out

INT-1 IRQ0

NMI Interrupt

Counter 1 Refresh Request

Gate

Always On

Clock In

1193 MHz(0SC12)

Out

Refresh Request

Counter 2

Gate

Programmable

Refresh Request

Clock In

Port 61h

Out

1193 MHz(OSC12)

8 MHz (BCLK)

Speaker

CPU Speed Control (SLOWH )

81 Interval Timer Address Map

Table 21 shows the IO address map of the interval timer counters

Table 21 Interval Timer IO Address Map

IO Port Address

040h

Timer 1 System Timer (Counter 0)

041h

Timer 1 Refresh Request (Counter 1)

042h

Timer 1 Speaker Tone (Counter 2)

043h

Timer 1 Control Word Register

048h

Timer 2 Fail-Safe Timer (Counter 0)

049h

Timer 2 Reserved

04Ah

Timer 2 CPU Speed Control (Counter 2)

04Bh

Timer 2 Control Word Register

Timer 1Counter 0 System Timer

This counter functions as the system timer by controlling the state of IRQ 0 and is typically programmed for

Mode 3 operation The counter produces a square wave with a period equal to the product of the counter

period (838 ns) and the initial count value The counter loads the initial count value one counter period after

software writes the count value to the counter IO address The counter initially asserts IRQ 0 and decre-

ments the count value by two each counter period The counter negates IRQ 0 when the count value reaches

0 It then reloads the initial count value and again decrements the initial count value by two each counter

period The counter then asserts IRQ 0 when the count value reaches ‘‘0’’ reloads the initial count value and

repeats the cycle alternately asserting and negating IRQ 0

147

82374EB Datasheet(PDF) 147 Page - Intel Corporation

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