PCM186X datasheet(36/115 Pages) TI1

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PLLCKIN

J.D

PLLC KIN

PLLCK

or PLLC K

PCM1860, PCM1862, PCM1864, PCM1864-Q1

SLASE55A – NOVEMBER 2014 – REVISED DECEMBER 2014

www.ti.com

Table 13. PCM1864 (4-Channel) PLL BCK Settings (continued)

BCK

PLL

DSP1

DSP1 Clock Divider 4

DSP1

DSP2 Clock Divider

ADC

ADC Clock Divider

Ratio

Freq.

Ratio

Frequenc

Configur

Clock

CH Mode

Clock

(MHz)

y (MHz)

ation

(MHz)

Source

Divider

Source

Divider

Source

Divider

4ch

2CH

256

49.152

512

98.304

P=15,R=1

98.304

PLL

49.152

PLL

6.144

PLL

, J=16,

D=0

10.12.4.5 PCM186x Software Programmable Devices ADC Non-Audio MCK PLL Mode

This mode is mainly used for systems driving TDM ports or systems where the MCK is not related to the audio

sampling rate. Examples may be where the Audio ADC needs to share a clock source with the central processor.

(This is commonly 12 MHz, 24 MHz or 27 MHz.)

Under these conditions, the automatic configuration register CLKDET_EN (Page 0, 0x20) should be set to 0, and

the PLL manually configured, using registers (Page 0, 0x28 - 0x2D). See PCM186x Software Programmable

Devices Manual PLL Calculation.

10.12.5 PCM186x Software Programmable Devices Manual PLL Calculation

The PCM186x has an on-chip PLL with fractional multiplication to generate the clock frequency required by the

audio ADC, Modulator and Digital Signal Processing blocks. The programmability of the PLL allows operation

from a wide variety of clocks that may be available in the system. The PLL input supports clocks varying from

1MHz to 50MHz and is register programmable to enable generation of required sampling rates with fine

precision.

The PLL by default is enabled because the on-chip fixed function DSPs require high clock rates to complete all

various decimation, mixing and level-detection functions. The PLL output clock PLLCK is given by Equation 1:

PLL Rate Calculation:

(1)

R = 1, 2, 3, 4, ….. 15, 16

J = 1, 2, 3, 4,...63, and D = 0000, 0001, 0002...9999

K = J.D

P = 1, 2, 3...15

R, J, D, and P are register programmable. J is the integer portion of K (the numbers to the left of the decimal

point), while D is the fractional portion of K (the numbers to the right of the decimal point, assuming four digits of

precision).

Examples:

If K = 8.5, then J = 8, D = 5000

If K = 7.12, then J = 7, D = 1200

If K = 14.03, then J = 14, D = 0300

If K = 6.0004, then J = 6, D = 0004

When the PLL is enabled and D = 0000, the following conditions must be satisfied:

1 MHz = (PLLCKIN / P) = 20 MHz

64 MHz < (PLLCK IN × K × R / P) < 100 MHz

1 = J = 63

When the PLL is enabled and D /= 0000, the following conditions must be satisfied:

6.667MHz = PLLCLK _IN / P = 20 MHz

64MHz < (PLLCK IN x K x R / P) < 100 MHz

4 = J = 11

R = 1

When the PLL is enabled,

fSref = (PLLCLK_IN × K × R) / (N × P) :

N is selected so that fSref × N = PLLCLK_IN × K × R / P is in the allowable range.

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Product Folder Links: PCM1860 PCM1862 PCM1864 PCM1864-Q1

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