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PCM186X Datasheet(PDF) 49 Page - Texas Instruments |
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PCM186X Datasheet(HTML) 49 Page - Texas Instruments |
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49 / 115 page  PCM1860, PCM1862, PCM1864, PCM1864-Q1 www.ti.com SLASE55A – NOVEMBER 2014 – REVISED DECEMBER 2014 Interrupt Controller (continued) The clock error status can be read in register CLK_ERR_STAT (Page.0 0x20). The clock detection logic is shown below: Table 21. Summary of Clock Detection Logic SCK BCK LRCK Result Action ACTIVE ACTIVE ACTIVE No Error Normal Operation ACTIVE ACTIVE HALT Clock Error Enter Clock Waiting State ACTIVE HALT ACTIVE Clock Error Enter Clock Waiting State ACTIVE HALT HALT Clock Error Enter SLEEP HALT ACTIVE ACTIVE No Error Enter BCK PLL Mode HALT ACTIVE HALT Clock Error Enter Clock Waiting State HALT HALT ACTIVE Clock Error Enter Clock Waiting State HALT HALT HALT Clock Error Enter SLEEP In addition, the device uses an on-chip oscillator to detect errors in the rate of present clocks. That logic is shown below: Table 22. Summary of Clock Error Logic SCK/LRCK Ratio BCK/LRCK Ratio LRCK Error Detect Action - - < 8kHz or > 192kHz fS error Enter Clock Waiting State Not 128 / 256 / Enter the clock waiting state, tie I2S - 8 / 16 / 32 / 44.1 / 48 kHz SCK error 384 / 512 / 768 output to 0 Not 128 / 256 / Enter the clock waiting state, tie I2S - 88.2 / 96kHz SCK error 384 / 512 output to 0 Enter the clock waiting state, tie I2S Not 128 / 256 - 176.4 / 192kHz SCK error output to 0 8 / 16 / 32 / 44.1 / 48 / 88.2 Enter the clock waiting state, tie I2S Not 256 / 64 / 48 / 32 BCK error / 96 / 174.6 / 196kHz output to 0 Enter the clock waiting state, tie I2S >192kHz fS error output to 0 In an application with a non-audio standard SCK coming into the product, the clock error detection on the SCK pin can be ignored by disabling the Auto Clock Detector (CLKDET_EN Page.0 0x20). Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 49 Product Folder Links: PCM1860 PCM1862 PCM1864 PCM1864-Q1 |
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