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UPD178024 Datasheet(PDF) 26 Page - NEC |
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UPD178024 Datasheet(HTML) 26 Page - NEC |
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26 / 56 page  26 µPD178023, 178024 Data Sheet U14126EJ1V0DS00 3.7 PLL Frequency Synthesizer Figure 3-11. Block Diagram of PLL Frequency Synthesizer Internal Bus Internal Bus PLL Mode Select Register (PLLMD) PLL Data Transfer Register (PLLNS) PLL NS0 PLL MD0 PLL MD1 PLL RF2 PLL RF1 PLL RF0 PLL UL0 PLL Reference Mode Register (PLLRF) PLL Unlock F/F Judge Register (PLLUL) PLL RF3 2 Input Select Block Programmable Divider Phase Comparator ( -DET) Unlock F/F Reference Frequency Generator 4.5 MHz 4 Charge Pump EO1 EO0 VCOH VCOL Mixer 2 fN fr PLL Data Register (PLLRL, PLLRH, PLLR0) φ Voltage Control Generator Lowpass Filter Note Note VCOL DMD VCOH DMD Note External circuit. |
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