UPD178024 datasheet(22/56 Pages) NEC

22 / 56 page

µPD178023, 178024

Data Sheet U14126EJ1V0DS00

Figure 3-5. Block Diagram of Watchdog Timer

OSTS2 OSTS1 OSTS0

WDCS2 WDCS1 WDCS0

RUN

WDTM4 WDTM3

Clock input

control circuit

Divided clock

select circuit

RUN

Divider circuit

fX/28

INTWDT

RESET

WDT mode signal

Watchdog timer clock

select register (WDCS)

Oscillation stabilization

time select register (OSTS)

Watchdog timer mode

Output

control

circuit

Division mode

select circuit

Internal bus

BEEP

CL02

BEEP

CL01

BEEP

CL00

BEEP0 clock select

BEEP0/P36

1 kHz

1.5 kHz

3 kHz

4 kHz

Output latch

(P36)

PM36

Selector

3.4 Buzzer Output Control Circuit

The buzzer output frequency is selected as follows.

• BEEP0 ... 1 kHz/1.5 kHz/3 kHz/4 kHz

Figure 3-6. Block Diagram of Buzzer Output Control Circuit (BEEP0)

UPD178024 Datasheet(PDF) 22 Page - NEC

UPD178024 Datasheet(HTML) 22 Page - NEC

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