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UPD178024 Datasheet(PDF) 9 Page - NEC |
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UPD178024 Datasheet(HTML) 9 Page - NEC |
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9 / 56 page  9 µPD178023, 178024 Data Sheet U14126EJ1V0DS00 BLOCK DIAGRAM Remark The internal ROM and RAM capacities differ depending on the product. 78K/0 CPU CORE ROM RAM 8-bit TIMER/ EVENT COUNTER50 8-bit TIMER/ EVENT COUNTER51 WATCHDOG TIMER BASIC TIMER SERIAL INTERFACE3 I 2C BUS INTERRUPT CONTROL UART0 BUZZER OUTPUT SYSTEM CONTROL VOLTAGE REGULATOR RESET CPU PERIPHERAL VOSC VCPU RESET X1 X2 VDDPORT GNDPORT VDD REGOSC REGCPU GND TI50/P33 TO50/P130 TI51/P34 TO51/P131 SI3/P70 SO3/P71 SCK3/P72 SDA0/P76 SCL0/P77 INTP0/P00- INTP4/P04 5 (RXD0)/P74 (TXD0)/P75 BEEP0/P36 PORT0 P00-P06 PORT1 PORT3 PORT4 PORT5 PORT6 PORT7 PORT12 PORT13 A/D CONVERTER FREQUENCY COUNTER PLL PLL VOLTAGE REGULATOR 7 6 8 8 8 8 8 6 3 6 P10-P15 P30-P37 P40-P47 P50-P57 P60-P67 P70-P77 P120-P125 P130-P132 ANI0/P10- ANI5/P15 AMIFC FMIFC EO0 EO1 VCOL VCOH VDDPLL GNDPLL IC |
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