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AN2620 Datasheet(PDF) 13 Page - STMicroelectronics |
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AN2620 Datasheet(HTML) 13 Page - STMicroelectronics |
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13 / 20 page ![]() AN2620 Board usage recommendation Doc ID 13883 Rev 3 13/20 4.1 External component selection for the ST1S10 demonstration board Figure 2 shows the typical application used to obtain an output voltage of 5 V. In order to obtain the needed output voltage we must choose the resistor divider according to the following formula: Equation 14 where VFB = 0.8 V and R2 suggested value is ~2 kΩ. 4.2 Inductor selection Due to the high frequency (900 kHz) it is possible to use a very small inductor value. We tested our device with an inductor value of 3.3 µH with very good efficiency performances. As the device is able to provide an operative output current of 3 A, we strongly recommend using inductors able to manage at least 4.4 A. 4.3 Capacitors selection It is possible to use any X5R or X7R ceramic capacitor ● C1 = 4.7 µF (ceramic) or higher ● C2 = 22 µF (ceramic) or higher, ESR=10 ~ 100 m Ω range ● C3 = 0.1 µF (ceramic) or higher It is possible to put several capacitors in parallel in order to reduce the equivalent series resistor and improve the ripple present in the output voltage. 4.4 Heavy capacitive load condition Thanks to the OCP and OVP circuit, the ST1S10 is strongly protected against short-circuit and overload damages. However, a highly capacitive load on the output may cause a difficult startup. This can be solved by using the modified application circuit shown in Figure 9 in which a minimum of 10 µF for C1 and a 4.7 µF ceramic capacitor for C3 are used. Moreover, for CLOAD >100 µF, it is needed to add the C4 capacitor in parallel to the upper voltage divider resistor (R1) as shown in Figure 9. The suggested value for C4 is 4.7 nF ~ 47 nF. Note that the C4 may impact the control loop response and should be added only when a capacitive load higher than 100 µF is present at all times. If the high capacitive load is variable or not present at any time, in addition to C4 it is advisable to increase the output ceramic capacitor C2 from 22 µF to 47 µF (or use 2 x 22 µF capacitors in parallel). Also in this case it is advisable to further increase the input capacitors with a minimum of 10 µF for C1 and a 4.7 µF ceramic capacitor for C3 as shown in Figure 10. V out V FB 1 R1 R2 -------- + ⋅ = |
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