AN2738 datasheet(30/54 Pages) STMICROELECTRONICS

30 / 54 page

Application example

AN2738

30/54

Doc ID 14589 Rev 2

the VGE up to the plateau voltage and the QGC required during the whole plateau phase.

This last amount of charge is also called the plateau charge. The time required to provide

the complete plateau charge is the Tfall time, and this is the same time necessary for

completing the VCE transition. For Ton time is intended the time delay between the

beginning of the gate charge and the full conduction of the IGBT (or MOSFET), when the

power switch current equals the full load current. So Tfall can be calculated as follows:

Equation 6

It is now possible to merge the equivalent gate driver output circuit reported in figures 24

and 25 and the considerations regarding the different gate charge phases in the total

equivalent circuit reported in Figure 27.

Figure 27.

Total equivalent circuit for the turn-on

From the above circuit the value of the transition times could be calculated (the following

formulae are related to the low side transition, but the same are suitable also for the high

side by exchanging “VCC” with “VBOOT-VOUT”):

Equation 7

Equation 8

CISS_min is used because when the VCE (or VDS) of the power IGBT (or MOSFET) is

maximum (equal to HVbus), CISS (which depends on the VCE) shows its minimum value.

During the turn-off of the power IGBT (or MOSFET), the behavior is the same as the turn-

on, but in reversed time order. In Figure 28, the gate charge characteristics and VCE vs. IC

curves are provided. The time required to sink the complete plateau charge is the Trise time,

while for Toff time is intended the time delay between the beginning of the gate charge and

the increase of Vce (or Vds) voltage.

fall

SOURCE

-----------------------

RGATE

RDSon_source

BOOT/VCC

Cge =

Qge

Vge_p

Vge

Isource

Ton

RGATE

RDSon_source

BOOT/VCC

Vge_p

Isource

Tfall

= Ciss_min

DS on

()

GATE

() C

ISSmin

VCC

GEP

–

----------------------------------

⎝⎠

⎛⎞

⋅⋅

FALL

SOURCE

-----------------------

DS on

()

GATE

()

VCC

GEP

–

--------------------------------------------------

⋅

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