LT1683 datasheet(16/24 Pages) LINER

16 / 24 page

LT1683

1683f

APPLICATIO S I FOR ATIO

So if we wanted to turn on at 20V with 2V of hysteresis:

−

1 39

0 1

1 39

23 4

1 39

0 1

1 39

175

•.

• .

•.

• .

•(

)

Resistor values could be altered further by adding Zeners

in the divider string. A resistor in series with SHDN pin

could further change hysteresis without changing turn on

voltage.

Frequency Compensation

Loop frequency compensation is accomplished by way of

a series RC network on the output of the error amplifier

(VC pin).

To prevent irregular switching, VC pin ripple should be

kept below 50mVP-P . Worst-case VC pin ripple occurs at

maximum output load current and will also be increased if

poor quality (high ESR) output capacitors are used. The

addition of a 0.0047

µF capacitor for CVC2 pin reduces

switching frequency ripple to only a few millivolts. A low

value for RVC will also reduce VC pin ripple, but loop phase

margin may be inadequate.

Setting Current Limit

The sense resistor sets the value for maximum operating

current. When the CS pin voltage is 0.1V the gate drivers

will immediately go low (no slew control). Therefore the

sense resistor value should be set to RS = 0.1V/ISW(PEAK),

where ISW(PEAK) is the peak current in the MOSFETs.

ISW(PEAK) will depend on the topology and component

values and tolerances. Certainly it should be set below the

saturation current value for the transformer.

If CS pin voltage is 0.22V in addition to the drivers going

low, VC and SS will be discharged to ground. This is to

provide additional protection in the event of a short circuit.

By discharging VC and SS the MOSFET will not be stressed

as hard on subsequent cycles since the current trip will be

set lower.

Turn off of the MOSFETs will normally be inhibited for

about 100ns at the start of every turn on cycle. This is to

prevent noise from interfering with normal operation of

the controller. This current sense blanking does not pre-

vent the outputs from be turned off in the event of a fault.

Slewing of the gate voltage effectively provides additional

blanking.

Traces to the SENSE resistor should be kept short and

wide to minimize resistance and inductance.

Soft-Start

The soft-start pin is used to provide control of switching

current during startup. The max voltage on the VC pin is

approximately the voltage on the SS pin. A current source

will linearly charge a capacitor on the SS pin. The VC pin

voltage will thus ramp also. The approximate time for the

voltage on these pins to ramp is (1.31V/9

µA) • CSS or

approximately 146ms per

µF.

Figure 6

VC PIN

1683 F06

RVC

CVC

0.01

µF

CVC2

4.7nF

Referring to Figure 6, the main pole is formed by capacitor

CVC and the output impedance of the error amplifier

(approximately 400k

Ω). The series resistor RVC creates a

“zero” which improves loop stability and transient re-

sponse. A second capacitor CVC2, typically one-tenth the

size of the main compensation capacitor, is sometimes

used to reduce the switching frequency ripple on the VC

pin. VC pin ripple is caused by output voltage ripple

attenuated by the output divider and multiplied by the error

amplifier. Without the second capacitor, VC pin ripple is:

Vgm R

CPINRIPPLE

RIPPLE

OUT

125

.•

•

where VRIPPLE = Output ripple (VP-P )

gm = Error amplifier transconductance

RVC = Series resistor on VC pin

VOUT = DC output voltage

LT1683 Datasheet(PDF) 16 Page - Linear Technology

LT1683 Datasheet(HTML) 16 Page - Linear Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Datasheet Download

Link URL