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LT1683

1683f

APPLICATIO S I FOR ATIO

Gate Driver Considerations

In general, the MOSFETs should be positioned as close to

the part as possible to minimize inductance.

When the part is active the gate drives will be pulled low to

less than 0.2V. When the part is off, the gate drives contain

a 40k resistor in series with a diode to ground that will offer

passive holdoff protection. If you are using some logic

level MOSFETs this might not be sufficient. A resistor may

be placed from gate to ground, however the value should

be reasonably high to minimize DC losses and possible AC

issues.

The gate drive source current comes from VIN. The sink

current exits through PGND. In general the decoupling cap

should be placed close to these two pins.

Switching Diodes

In general, switching diodes should be Schottky diodes.

Size and breakdown voltage depend on the specific con-

verter. A lower forward drop will improve converter effi-

ciency. No other special requirements are needed.

PCB Layout Considerations

As with any switcher careful consideration should be given

to PC board layout. Because this part reduces high fre-

quency EMI the board layout is less critical, however high

currents and voltages still produce the need for careful

board layout to eliminate poor and erratic performance.

Basic Considerations

Keep the high current loops physically small in area. The

main loops are shown in Figure 8: the power switch loops

(A and B) and the rectifier loop (C and D). These loops can

be kept small by physically keeping the components close

to one another. In addition, connection traces should be

kept wide to lower resistance and inductances. Compo-

nents should be placed to minimize connecting paths.

Careful attention to ground connections must also be

maintained. Without getting into elaborate detail be care-

ful that currents from different high current loops do not

get coupled into the ground paths of other loops. Using

singular points of connection for the grounds is the best

way to do this. The two major points of connection are the

bottom of the input decoupling cap and the bottom of the

output decoupling cap. Typically the sense resistor device

PGND and device GND will tie to the bottom of the input

cap.

There are two other loops to pay attention to. The current

slew involves a high bandwidth control that goes through

the MOSFET switch, the sense resistor and into the CS pin

of the part and out the GATE pin to the MOSFET. Trace

inductance and resistance should be kept low on the GATE

drive trace. The CS trace should have low inductance. The

sense resistor should be physically close to PGND and the

MOSFETs’ sources.

Finally care should be taken with the CAP A, CAP B pins.

The part will tolerate stray capacitance to ground on these

pins (<5pF) however stray capacitance to the respective

drains should be minimized. This path would provide an

alternate capacitive path for the voltage slew.

More Help

AN70 contains information about low noise switchers and

measurement of noise and should be consulted. AN19 and

AN29 also have general knowledge concerning switching

regulators. Also, our Application Department is always

ready to lend a helping hand.

Figure 8

1683 F08

CIN

COUT

GATE A

GATE B

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