UPD754304GS datasheet(21/74 Pages) NEC

21 / 74 page

µPD754302, 754304, 754302(A), 754304(A)

Note Instruction execution

Remarks 1.

fX = System clock frequency

Φ = CPU clock

PCC: Processor Clock Control Register

One clock cycle (tCY) of the CPU clock is equal to one machine cycle of the instruction.

System

clock oscillator

HALTNote

STOPNote

PCC0

PCC1

PCC2

PCC3

PCC2,

PCC3

Clear

STOP

F/F

Oscillation

stop

HALT F/F

Wait signal from BT

RESET signal

Standby release signal from

interrupt control circuit

· CPU

· INT0 noise eliminator

· Clock output circuit

1/4

Divider

1/1 to 1/4096

Divider

1/2 1/4 1/16

· Basic interval timer (BT)

· Timer/event counters 0, 1

· Serial interface

· INT0 noise eliminator

· Clock output circuit

PCC

Selector

6.2 Clock Generator

•

Clock generator configuration

The clock generator provides the clock signals to the CPU and peripheral hardware and its configuration

is shown in Figure 6-1.

The operation of the clock generator is set with the processor clock control register (PCC).

The instruction execution time can be changed.

• 0.95, 1.91, 3.81, 15.3

µs (system clock operating at 4.19 MHz)

• 0.67, 1.33, 2.67, 10.7

µs (system clock operating at 6.0 MHz)

Figure 6-1. Clock Generator Block Diagram

UPD754304GS Datasheet(PDF) 21 Page - NEC

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