UPD78014 datasheet(4/62 Pages) NEC

4 / 62 page

µPD78001B(A), 78002B(A)

OVERVIEW OF FUNCTION

Item

ROM

Internal high-

speed RAM

8K bytes

16K bytes

64K bytes

8 bits

× 32 registers (8 bits × 8 registers × 4 banks)

On-chip instruction execution time cycle modification function

0.4

µs/0.8 µs/1.6 µs/3.2 µs/6.4 µs (at 10.0 MHz operation)

122

µs (at 32.768 kHz operation)

• 16-bit operation

• Bit manipulation (set, reset, test, boolean operation)

• BCD correction, etc.

Total

: 53

• CMOS input

: 02

• CMOS I/O

: 47

• N-channel open-drain I/O

(15 V withstand voltage)

: 04

• 3-wire/SBI/2-wire mode selectable

• 8-bit timer/event counter

: 2 channels

• Watch timer

: 1 channel

• Watchdog timer

: 1 channel

39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz (at main system clock 10.0 MHz operation),

32.768 kHz (at subsystem clock 32.768 kHz operation)

2.4 kHz, 4.9 kHz, 9.8 kHz (at main system clock 10.0 MHz operation)

Internal : 5

External : 4

Internal : 1

External : 1

VDD = 2.7 to 6.0 V

–40 to +85

°C

• 64-pin plastic shrink DIP (750 mil)

• 64-pin plastic QFP (s

s14 mm)

256 bytes

384 bytes

When main system

clock selected

When subsystem

clock selected

Maskable

interrupts

Non-maskable

interrupt

Software

interrupt

Product Name

µPD78001B(A)

µPD78002B(A)

Internal

memory

Memory space

General registers

Instruction cycle

Instruction set

I/O ports

Serial interface

Timer

Timer output

Clock output

Buzzer output

Vectored

interrupts

Test input

Operating voltage range

Operating ambient

temperature range

Package

UPD78014 Datasheet(PDF) 4 Page - NEC

UPD78014 Datasheet(HTML) 4 Page - NEC

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