MAX186AEAP datasheet(5/24 Pages) MAXIM

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Note 1: Tested at VDD = 5.0V; VSS = 0V; unipolar input mode.

Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has

been calibrated.

Note 3: MAX186 – internal reference, offset nulled; MAX188 – external reference (VREF = +4.096V), offset nulled.

Note 4: Ground on-channel; sine wave applied to all off channels.

Note 5: Conversion time defined as the number of clock cycles times the clock period; clock has 50% duty cycle.

Note 6: Guaranteed by design. Not subject to production testing.

Note 7: External load should not change during conversion for specified accuracy.

Note 8: Measured at VSUPPLY +5% and VSUPPLY -5% only.

Note 9: The common-mode range for the analog inputs is from VSS to VDD.

Low-Power, 8-Channel,

Serial 12-Bit ADCs

_______________________________________________________________________________________

PARAMETER

SYMBOL

CONDITIONS

UNITS

Positive Supply Rejection

(Note 8)

PSR

±0.06

±0.5

Negative Supply Rejection

(Note 8)

PSR

VSS = -5V ±5%; external reference, 4.096V;

full-scale input

±0.01

±0.5

ELECTRICAL CHARACTERISTICS (continued)

(VDD = 5V ±5%; VSS = 0V or -5V; fCLK = 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); MAX186—

4.7µF capacitor at VREF pin; MAX188—external reference, VREF = 4.096V applied to VREF pin; TA = TMIN to TMAX, unless otherwise

noted.)

TIMING CHARACTERISTICS

(VDD = 5V ±5%; VSS =0V or -5V, TA = TMIN to TMAX, unless otherwise noted.)

PARAMETER

SYMBOL

CONDITIONS

UNITS

SCLK Pulse Width Low

tCL

200

SCLK Fall to SSTRB

tSSTRB

CLOAD = 100pF

200

tSDV

External clock mode only, CLOAD = 100pF

200

tSTR

External clock mode only, CLOAD = 100pF

200

tSCK

Internal clock mode only

Acquisition Time

tAZ

1.5

µs

DIN to SCLK Setup

tDS

100

DIN to SCLK Hold

tDH

CLOAD = 100pF

150

SCLK Fall to Output Data Valid

tDO

200

CS Fall to Output Enable

tDV

CLOAD = 100pF

100

CS Rise to Output Disable

tTR

CLOAD = 100pF

100

CS to SCLK Rise Setup

tCSS

100

CS to SCLK Rise Hold

tCSH

SCLK Pulse Width High

tCH

200

MAX18_ _C/E

MAX18_ _M

SSTRB Rise to SCLK Rise

(Note 6)

CS Fall to SSTRB Output Enable

(Note 6)

VDD = 5V ±5%; external reference, 4.096V;

full-scale input

MIN

TYP

MAX

MIN

TYP

MAX

CS Rise to SSTRB Output Disable

(Note 6)

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