OPA625 datasheet(33/44 Pages) TI

33 / 44 page

Time (ns)

500

1000

1500

2000

-2

-1.5

-1

-0.5

0.5

1.5

Time (ns)

500

1000

1500

2000

-2

-1.5

-1

-0.5

0.5

1.5

FLT

15 C

OPA625, OPA2625

www.ti.com

SBOS688 – APRIL 2015

9.2.2.2 Detailed Design Procedure

An ADC input driver circuit mainly consists of two parts: a driving amplifier and a fly-wheel RC filter. The amplifier

is used for signal conditioning of the input voltage and its low output impedance provides a buffer between the

signal source and the ADC input. The RC filter helps attenuate the sampling charge-injection from the switched-

capacitor input stage of the ADC as well as acts as an anti-aliasing filter to band-limit the wideband noise

contributed by the front-end circuit. The design of the ADC input driver involves optimizing the bandwidth of the

circuit, driven primarily by the following requirements:

•

The RFLTCFLT filter bandwidth should be low to band-limit the noise fed into the input of the ADC thereby

increasing the signal-to-noise ratio (SNR) of the system.

•

The overall system bandwidth should be large enough to accommodate optimal settling of the input signal at

the ADC input before the start of conversion.

CFLT is chosen based upon Equation 7 . CFLT is chosen to be 1 nF.

(7)

Connecting a 1-nF capacitor directly to the output of the OPA625 would degrade the OPA625 phase margin and

result in stability and settling time problems. To properly drive the 1-nF capacitor, a series resistor, RFLT, is used

to isolate the capacitor, CFLT, from the OPA625. RFLT must be sized based upon several constraints. To

determination a suitable value for RFLT, the system designer must consider the impact upon the THD due to the

voltage divider effect from RFLT reacting with the switch resistance, RSW, of the ADC input circuit as well as the

impact of the output impedance upon amplifier stability. In this example 12.4-

Ω resistors are selected. In this

design example, Figure 15 can be used to estimate a suitable value for RISO. RISO represents the total resistance

in series with CFLT, which in this example is equivalent to 2 × RFLT.

For step-by-step design procedure, circuit schematics, bill of materials, printed circuit board (PCB) files,

simulation results, and test results, refer to TI Precision Design, TIDU012, "Power-optimized 16-bit 1MSPS

Data Acquisition Block for Lowest Distortion and Noise Reference Design".

9.2.2.3 Application Curves

Figure 77 illustrates the performance of the circuit shown in Figure 75.

Figure 77. Positive Transient Response for Figure 75

Figure 78. Negative Transient Response for Figure 75

Submit Documentation Feedback

Product Folder Links: OPA625 OPA2625

OPA625 Datasheet(PDF) 33 Page - Texas Instruments

OPA625 Datasheet(HTML) 33 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

Datasheet Download

Link URL