V

OUT

L

SW

VIN

FB

GND

EN

/PG

V

IN

GND

GND

C

IN

R1

R2

R3

Bottom layer

Top layer

C

OUT

TLV62565, TLV62566

SLVSBC1C – OCTOBER 2013 – REVISED JULY 2015

www.ti.com

13 Layout

13.1 Layout Guidelines

The PCB layout is an important step to maintain the high performance of the TLV62565 devices.

•

The input/output capacitors and the inductor should be placed as close as possible to the IC.

•

This keeps the traces short. Routing these traces direct and wide results in low trace resistance and low

parasitic inductance.

•

A common power GND should be used.

•

The low side of the input and output capacitors must be connected properly to the power GND to avoid a

GND potential shift.

•

The sense traces connected to FB is a signal trace .

•

Special care should be taken to avoid noise being induced. By a direct routing, parasitic inductance can be

kept small.

•

GND layers might be used for shielding.

•

Keep these traces away from SW nodes.

13.2 Layout Example

Note: PG connected to VIN via R3, EN direct connect to VIN

Figure 24. TLV62565 Layout

13.3 Thermal Considerations

Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires

special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow,

convection surfaces, and the presence of other heat-generating components affect the power dissipation limits of

a given component.

Two basic approaches for enhancing thermal performance are listed below:

•

Improving the power dissipation capability of the PCB design

•

Introducing airflow in the system

For more details on how to use the thermal parameters, see the application notes: Thermal Characteristics

Application Notes SZZA017 and SPRA953.

18

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