SM8212 datasheet(13/32 Pages) NPC

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NIPPON PRECISION CIRCUITS-13

SM8212B

(4) Lock mode

PREAMBLE

Mode

LOCK

Mode

IDLE

Mode

POWER-ON

Mode

Figure 7. Operating mode transition diagram

A: After reset, parameters/addresses are set and start command

is issued.

B: Rate error or, within a fixed period, preamble pattern/sync

code not detected.

C: Preamble pattern detected.

D: Sync code detected 1 cycle immediately after transfer from

lock mode.

E: Sync code not detected on 2 consecutive attempts

F: Same as E, but preamble detected on the second attempt.

G: Sync code detected.

H: Parameters/addresses are set and start command is issued

from preamble/idle/lock mode.

If the sync code is detected during the preamble period,

device operation transfers to lock mode and BS1 goes

LOW. BS1 then goes HIGH again under frame timing,

where the frame number is set by flags FF0 to FF2, and the

32 addresses are compared with ID-ROM (If the frame

number is 0, BS1 stays HIGH). If errors of 2 bits or less

occur, the address is still recognized. Since there are two

code words per frame, this check is done twice.

When one of the 32 addresses does not match, BS1 goes

LOW and the device waits for the next frame or sync code

receive timing. If the sync code is still not detected after

two consecutive attempts, device operation transfers to idle

mode, except during message reception where operation

stays in lock mode. If the sync code is not detected on the

second attempt, but instead a pattern forming a preamble

is detected, device operation transfers to preamble mode

and not idle mode (preamble mode is more advantageous

for sync code detection).

When one of the 32 addresses does match, ATTN goes

LOW and the address information (see “Data/Flags” sec-

tion) is transmitted to the CPU on SDO in sync with the

SCK clock.

When the address information is confirmed to be a mes-

sage, BS1 is held HIGH and the message is received. The

received message is stored in a buffer as 32-bit error-cor-

rected information (see “Data/Flags” section), then ATTN

goes LOW and the data is transmitted to the CPU on

SDO in sync with the SCK clock.

When the address and message is received, ATTN should

be held LOW while the data is output on SDO.

When an incoming message spans two or more batches,

additional sync code detection occurs during sync code

receive timing.

Message reception can be selected to end when either an

address code or idle code is detected, or when interrupted

using the decoder set command BREAK input. This selec-

tion is made when setting parameters that will not cause

the message to terminate. If the BREAK mode is selected,

even if an address other than the self address (MSB = 0) is

received during message reception, reception continues

without interruption and address data is sent to the micro-

controller using the same data handling as for a message. In

this case, reception can only be interrupted by a BREAK

input signal from the microcontroller.

In either of the above cases, message reception ends if an

end-of-message signal is sent. (Except MSB=0 but self

address, no BREAK input)

When message reception ends, BS1 goes LOW and the

device waits for either the address detect timing of the next

frame or the sync code receive timing.

When sending data from the decoder to the microcon-

troller, the SCK clock frequency should not be less than

512, (1200), [2400] Hz. If this occurs, the SCK counter is

reinitialized. This function, however, does make restoring

operation easy even if this or another clock is accidentally

input.

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