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SM8212 Datasheet(PDF) 19 Page - Nippon Precision Circuits Inc

Part # SM8212
Description  POCSAG Decoder For Multiframe Pagers
PDF  32 Pages
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Manufacturer  NPC [Nippon Precision Circuits Inc]
Direct Link  http://www.npc.co.jp/en
Logo NPC - Nippon Precision Circuits Inc

SM8212 Datasheet(HTML) 19 Page - Nippon Precision Circuits Inc

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NIPPON PRECISION CIRCUITS-19
SM8212B
8. Miscellaneous Interface Pins
(1) SIGNAL
(2) XT, XTN
(3) CLKO
(4) RSTN
(5) AREA
Crystal oscillator element connection pins.
The SM8212B operates at 76.8 kHz system clock speed,
and this clock can be provided simply by connecting a crys-
tal element between XT and XTN. The oscillator amplifi-
er, feedback resistance and oscillator capacitance are all
built-in.
In this case, XTN should not be used as a clock to drive
an external device. Also, a 1000 pF to 0.1 µF capacitor
should be connected between XVSS and VDD.
Clock output pin. The clock output can be used as a
CPU sleep clock or melody IC (SM1124 series) clock.
The output clock frequency, 76.8 or 38.4 kHz, is selected
using the decoder parameter set command.
Decoder IC internal initialization reset pin. It also func-
tions as an oscillator start-up booster (current source)
immediately after power is applied to speed up oscillator
stabilization.
This pin goes HIGH for
≥ 1 second when a sync code is
detected with 2 or less random bit errors in preamble, lock
or idle mode sync code detection timing.
During intermittent-duty CPU operation, monitoring
this pin is useful for out-of-range signal strength.
However, even if a sync code is detected, this pin is not
held HIGH for
≥ 1 second if 2 consecutive sync codes
could not be detected, or under the following situations in
1200 and 2400 bps modes.
When the second of 2 consecutive sync codes could
not be detected but a 6-bit preamble is detected and
preamble continues.
When operation transfers from lock mode to idle
mode and then to preamble mode. Note that if opera-
tion stays in idle mode after transfer from lock mode,
this pin goes HIGH for
≥ 1 second.
NRZ-format signal input pin, with built-in noise can-
celler filter.
Current pager systems operate at 3 baud rates (512, 1200
and 2400 bps). In conventional systems, the RF stage LPF
time constants are changed in response to the baud rate in
order to get the best possible reception. However, this
requires changing the external components which results in
increased product operating costs.
The SM8212B, however, performs digital processing on
the input signal which allows the 3 baud rates to be cov-
ered without the need to substitute RF stage LPF compo-
nents. The side effect of this digital filter processing is a
small probability of rate errors occurring.
Digital processing can be turned ON/OFF using flags.
When turned ON, there are 4 filter constant settings that
can be selected to obtain the best possible reception condi-
tions in a flexible manner (see “Parameter Flags” section).



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