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SM8580 Datasheet(PDF) 11 Page - Nippon Precision Circuits Inc |
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SM8580 Datasheet(HTML) 11 Page - Nippon Precision Circuits Inc |
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11 / 23 page  SM8580AM NIPPON PRECISION CIRCUITS—11 FUNCTIONAL DESCRIPTION Register Tables Bank 0 (clock, calendar registers) Bank 1 (alarm, FOUT registers) Bank 2 (digital correction, timer registers) s All bits in register F and bits 2 to 3 in register E are common to all register banks. s When alarm interrupts are not used, registers 0 to 8 in bank 1 can be used as RAM (total 36 bits). s When timer interrupts are not used, registers 4 to 5 in bank 2 can be used as RAM (total 8 bits). s When digital correction is not used, registers 0 to 1 in bank 2 can be used as RAM, excluding bit 3 (DT_ON) in register 1 (total 7 bits). s The BUSY/ADJ bit function is BUSY when read- ing, and ADJ when writing. s The BUSY flag is set to 1 an interval of 244µs before clock counter update timing. s Registers 6 and 7 in bank 2 are read-only registers, and cannot be written to. s When power is applied, all register bits are unde- fined, with the exception of bits FOS, TEST and TEMP. Accordingly, these bits need to be initial- ized. TEST and TEMP are automatically reset to 0 and FOS is automatically reset to 1 when power is applied. s Bits marked # are all read-only bits fixed to 0. These bits cannot be written to. s Bits marked * can be used as RAM bits. A d dress Register Bit 3 Bit 2 Bit 1 Bit 0 0 Second registers 8421 1 F O S 40 20 10 2 M i nute registers 8421 3 # 40 20 10 4 Hour registers 8421 5# # 2 0 1 0 6 D a y of week register #421 7 Date registers 8421 8# # 2 0 1 0 9 Month registers 8421 A ### 1 0 B Year registers 8421 C 8 04 02 01 0 D 800 400 200 100 E TEST TEMP 2000 1000 F Control register Bank SEL1 Bank SEL0 ST O P B USY/ ADJ A d dress Register Bit 3 Bit 2 Bit 1 Bit 0 0 Second registers 8421 1 A E 4 02 01 0 2 M i nute registers 8421 3 A E 4 02 01 0 4 Hour registers 8421 5 A E * 20 10 6 D a y of week register A E 421 7 Date registers 8421 8 A E * 20 10 9 – **** A – **** B CE1 control CTEMP CDT_ON * * C FOUT divider set register # FD2 FD1 FD0 D FOUT frequency set register FE # FD4 FD3 E Alarm control TEST TEMP A F A I E F Control register Bank SEL1 Bank SEL0 ST O P B USY/ ADJ A d dress Register Bit 3 Bit 2 Bit 1 Bit 0 0 Digital correction registers DT3 DT2 DT1 DT0 1 DT_ON D T 6 D T 5 D T 4 2 – #### 3 – #### 4 Timer counter set registers 8421 5 128 64 32 16 6 Timer counter output registers 8421 7 128 64 32 16 8 Timer setting T E TI/TP T D 1 T D 0 9 – #### A – #### B – **** C – **** D – **** E Timer control TEST TEMP T F TIE F Control register Bank SEL1 Bank SEL0 ST O P B USY/ ADJ |
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