SM8580 datasheet(16/23 Pages) NPC

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SM8580AM

NIPPON PRECISION CIRCUITS—16

Timer Registers (Bank 2, Registers 4 to 8, E)

Timer control registers (registers 8, E)

TE bit (timer enable)

Timer countdown stop/start control bit.

When set to 1, the timer starts counting down.

When set to 0 during countdown, the timer stops.

TF bit (timer ﬂag)

The timer ﬂag is set to 1 when the timer counter

counts down to zero, occurring a timer event. It is

held at 1 until 0 is written to this bit. A 1 cannot be

written to TF.

TIE bit (timer interrupt enable)

This bit enables the timer interrupt output on

TIRQN when a timer event is occurred. If the TIE

is not set to 1, then no output occurs even if the TF

bit is set to 1. The TIRQN output is high imped-

ance when TIE is set to 0.

TI/TP bit (level/periodic interrupt mode select bit)

Sets the timer interrupt signal output mode.

The SM8580AM supports two timer function

modes.

• TI/TP = 0 (level interrupt mode)

When a timer interrupt is occurred, TIRQN

goes LOW (if TIE = 1) and TF is set to 1.

TIRQN remains LOW and TF is held at 1 until

a 0 is written to the TF bit.

The timer operates by counting down until the

data is zero, then the TE bit is cleared and the

count stops automatically. However, if the timer

is started when the TF bit is 1, then the TE bit is

not cleared. The timer count register contents

remain zero after the count down stops.

• TI/TP = 1 (periodic interrupt mode)

When a timer interrupt is occurred, TIRQN

goes LOW (if TIE = 1) and TF is set to 1.

TIRQN subsequently goes high impedance

after a ﬁxed interval, but TF is held at 1 until a 0

is written to the TF bit.

The timer operates by counting down until the

data is zero, then the timer register data is

reloaded automatically after a ﬁxed interval,

and the countdown restarts. This mode can be

used as a repetitive interval timer.

Timer source clock set register (register 8)

The register 8 bits 0 and 1 set the timer source

clock to one of four frequencies listed in the fol-

lowing table.

Bank

A d dress

Bit 3

Bit 2

Bit 1

Bit 0

Timer setting

T E

TI/TP

Timer control

T F

TIE

Bank

A d dress

Bit 3

Bit 2

Bit 1

Bit 0

Timer setting

T D 1

T D 0

T D 1

T D 0

Timer source clock

4096Hz

64Hz

1Hz

1/60Hz (1 minute)

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