SM8580 datasheet(18/23 Pages) NPC

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SM8580AM

NIPPON PRECISION CIRCUITS—18

CE1 Control Register (Bank 1, Register B)

This register determines whether the temperature

sensor function and digital correction function in

combination with the CE1 input pin. CTEMP

determines the temperature sensor operation, and

CDT_ON determines the digital correction func-

tion operation.

CTEMP bit

When CTEMP is set to 0, the temperature sensor

operates only when the CE1 pin is HIGH.

When CTEMP is set to 1, the temperature sensor

operates without any relationship to the CE1 input

state.

Note that the temperature sensor operation also

depends on the bank 2 TEMP bit to be active.

CDT_ON bit

When CDT_ON is set to 0, the digital correction

function operates only when the CE1 pin is HIGH.

When CDT_ON is set to 1, the digital correction

function operates without any relationship to the

CE1 input state.

Note that the digital correction function also

depends on the bank 2 DT_ON bit to be active.

Function operation tables

Frequency Set Registers (Bank 1, Registers C, D)

FD3, FD4 bit

FOUT source clock frequency set bits.

FD0 to FD2 bits

Frequency divider set bits for the FOUT source

clock set by FD3 and FD4.

FE bit

FOUT frequency signal set by FD0 to FD4 output

enable bit.

When FCON is HIGH and FE is set to 1, then the

frequency signal set by FD0 to FD4 is output on

FOUT. When FE is set to 0, the FOUT output is

high impedance.

When FCON is LOW, a standard 32.768kHz sig-

nal is output on FOUT without reference to the

settings in the C and D registers.

Bank

A d dress

Bit 3

Bit 2

Bit 1

Bit 0

CE1 control

CTEMP

CDT_ON

CE1 pin

CTEMP bit

TEMP bit

Temperature

sensor

××

Not operating

L O W

Not operating

HIGH

O p e rating

L O W

O p e rating

HIGH

O p e rating

CE1 pin

CDT_ON bit

DT_ON bit

Digital

correction

××

Not operating

L O W

Not operating

HIGH

O p e rating

L O W

O p e rating

HIGH

O p e rating

Bank

A d dress

Bit 3

Bit 2

Bit 1

Bit 0

FOUT divider set register

F D 2

F D 1

F D 0

FOUT frequency set register

F E

F D 4

F D 3

F D 4

F D 3

Source clock

32768Hz

1024Hz

32Hz

1Hz

FD2

FD1

FD0

Frequenc y divider

ratio

FOUT output duty

1/1

1/2

1/3

1/6

1/2

1/5

1/10

1/2

1/15

1/3

1/30

1/2

FD2

FD1

FD0

Frequenc y divider

ratio

FOUT output duty

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